Xen devel - Feb 2009 - [PATCH]xend: fix a typo in pci.py

The PCI_EXP_TYPE_PCI_BRIDGE should be PCI_EXP_FLAGS_TYPE here.
Also a tiny fix to the python comment.

Signed-off-by: Dexuan Cui <dexuan.cui@intel.com>


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Cui, Dexuan wrote:
> The PCI_EXP_TYPE_PCI_BRIDGE should be PCI_EXP_FLAGS_TYPE here.
> Also a tiny fix to the python comment.
Please ignore the patch of the previous mail and use the attachments of this
mail:

[01_fix_d3d0.patch]
Fix some mistakes in tools/python/xend/util/pci.py
1) PCI_PM_CTRL_NO_SOFT_RESET: this is bit3 of PMCSR(Power Management
Control/Status). It should be 8. This bit means a device''s capability
of not doing an internal reset across D3hot/D0.
If the bit is 1, there shall be no reset across D3hot/D0, so we should not use
it as a method to reset device.
2) When performing reset, we should sleep at least 100ms; in current code,
it''s incorrect somewhere we sleep 0.2s and somewhere 0.01s.
3) In detect_dev_info(), fix a typo: PCI_EXP_TYPE_PCI_BRIDG ->
PCI_EXP_FLAGS_TYPE.
4) fix a small typo in the comment of transform_list().

[02_fix_xen_no_soft_reset.patch]
Fix the definition of PCI_PM_CTRL_NO_SOFT_RESET. This is bit3 of PMCSR(Power
Management Control/Status). It should be 8.

[03_fix_dom0_no_soft_reset.patch]
Fix the definition of PCI_PM_CTRL_NO_SOFT_RESET. This is bit3 of PMCSR(Power
Management Control/Status). It should be 8.


Signed-off-by: Dexuan Cui <dexuan.cui@intel.com>





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Cui, Dexuan writes:
> 2) When performing reset, we should sleep at least 100ms; in current code,
it''s incorrect somewhere we sleep 0.2s and somewhere 0.01s.
As long as I read "PCI Bus Power Management Interface Spec Rev 1.2",
the state transition recovery time across D3hot/D0 is 10ms.
Is it really neeeded to sleep 100ms?
In the case of FLR, 100ms should be necessary.

Thanks,
Kouya

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Hi Kouya,
Thanks for pointing this out. I didn't remember the time correctly.  :-)
I'll update the patch.

Thanks,
-- Dexuan

-----Original Message-----
From: Kouya Shimura [mailto:kouya@jp.fujitsu.com] 
Sent: 2009年3月2日 9:21
To: Cui, Dexuan
Cc: Keir Fraser; xen-devel@lists.xensource.com
Subject: Re: [Xen-devel] RE: [PATCH]xend: fix a typo in pci.py

Cui, Dexuan writes:
> 2) When performing reset, we should sleep at least 100ms; in current code,
it's incorrect somewhere we sleep 0.2s and somewhere 0.01s.
As long as I read "PCI Bus Power Management Interface Spec Rev 1.2",
the state transition recovery time across D3hot/D0 is 10ms.
Is it really neeeded to sleep 100ms?
In the case of FLR, 100ms should be necessary.

Thanks,
Kouya

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Xen-devel@lists.xensource.com
http://lists.xensource.com/xen-devel

Hi Keir,
For the first patch, please use the attached new version: 01_new_fix_d3d0.patch.
This new version keeps the correct 0.01s recovery time for D3hot/D0 transition
(in the previous version, it was changed to 0.1s by accident).

Thanks,
-- Dexuan

-----Original Message-----
From: Cui, Dexuan 
Sent: 2009年2月27日 18:31
To: Keir Fraser; xen-devel@lists.xensource.com
Subject: RE: [PATCH]xend: fix a typo in pci.py

Cui, Dexuan wrote:
> The PCI_EXP_TYPE_PCI_BRIDGE should be PCI_EXP_FLAGS_TYPE here.
> Also a tiny fix to the python comment.
Please ignore the patch of the previous mail and use the attachments of this
mail:

[01_fix_d3d0.patch]
Fix some mistakes in tools/python/xend/util/pci.py
1) PCI_PM_CTRL_NO_SOFT_RESET: this is bit3 of PMCSR(Power Management
Control/Status). It should be 8. This bit means a device's capability of not
doing an internal reset across D3hot/D0.
If the bit is 1, there shall be no reset across D3hot/D0, so we should not use
it as a method to reset device.
2) When performing reset, we should sleep at least 100ms; in current code,
it's incorrect somewhere we sleep 0.2s and somewhere 0.01s.
3) In detect_dev_info(), fix a typo: PCI_EXP_TYPE_PCI_BRIDG ->
PCI_EXP_FLAGS_TYPE.
4) fix a small typo in the comment of transform_list().

[02_fix_xen_no_soft_reset.patch]
Fix the definition of PCI_PM_CTRL_NO_SOFT_RESET. This is bit3 of PMCSR(Power
Management Control/Status). It should be 8.

[03_fix_dom0_no_soft_reset.patch]
Fix the definition of PCI_PM_CTRL_NO_SOFT_RESET. This is bit3 of PMCSR(Power
Management Control/Status). It should be 8.


Signed-off-by: Dexuan Cui <dexuan.cui@intel.com>



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