llvm dev - Apr 2021 - Matching BlockAddress DAG Nodes in TableGen

Hi:


I've written the following TableGen pattern matching code in my .td:


```
def : Pat<(set GP64:$dst,blockaddress:$tba),(i64 (MOVR8
tblockaddress:$tba))&gt;;
```
Which I assume means it would match the following DAG Node:


````
i64 XX = BlockAddress(@func, at BB) 0
````


but TableGen asserted out with&nbsp;


```
Assertion failed: (getOperator()-&gt;isSubClassOf("SDNodeXForm")
&amp;&amp; "Unknown node type!"), function
ApplyTypeConstraints, file LLVM/llvm/utils/TableGen/CodeGenDAGPatterns.cpp, line
2618.
```




Then I tried to custom lower BlockAddress nodes with custom ISD, yielding the
following DAG Node:


```
t162: i64 = LOADBLOCKADDRESS TargetBlockAddress:i64<@main, %odd.i18&gt; 0
```


then I tried to match this DAG Node in TableGen:




```
def SDT_LOADBLOCKADDRESS :
SDTypeProfile<1,1,[SDTCisInt<0&gt;,SDTCisVT<1,i64&gt;]&gt;;
def _LOADBLOCKADDRESS :
SDNode<"CUSTOMISD::LOADBLOCKADDRESS",SDT_LOADBLOCKADDRESS,[SDNPHasChain]&gt;;

...
def : Pat<(i64 (_LOADBLOCKADDRESS tblockaddress:$tba)),(i64 (MOVXI8
tblockaddress:$tba))&gt;;
```


Which failed when matching opcode&nbsp;OPC_RecordChild1
```
unsigned ChildNo = Opcode-OPC_RecordChild0;
&nbsp; &nbsp; &nbsp; if (ChildNo &gt;= N.getNumOperands())
&nbsp; &nbsp; &nbsp; &nbsp; break; &nbsp;// Match fails if
out of range child #.

```


due to ChildNo (1) &gt;= N.getNumOperands()




Zhang
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 For the custom lowering method, removing the extra SDNPHasChain
resolved the issue. However I still don't understand why the first pattern
matching method didn't work
 
------------------ Original ------------------
From: &nbsp;"llvm-dev"<llvm-dev at lists.llvm.org&gt;;
Date: &nbsp;Thu, Apr 1, 2021 11:10 AM
To: &nbsp;"llvm-dev"<llvm-dev at lists.llvm.org&gt;; 

Subject: &nbsp;[llvm-dev] Matching BlockAddress DAG Nodes in TableGen

&nbsp;

Hi:


I've written the following TableGen pattern matching code in my .td:


```
def : Pat<(set GP64:$dst,blockaddress:$tba),(i64 (MOVR8
tblockaddress:$tba))&gt;;
```
Which I assume means it would match the following DAG Node:


````
i64 XX = BlockAddress(@func, at BB) 0
````


but TableGen asserted out with 


```
Assertion failed: (getOperator()-&gt;isSubClassOf("SDNodeXForm")
&amp;&amp; "Unknown node type!"), function
ApplyTypeConstraints, file LLVM/llvm/utils/TableGen/CodeGenDAGPatterns.cpp, line
2618.
```




Then I tried to custom lower BlockAddress nodes with custom ISD, yielding the
following DAG Node:


```
t162: i64 = LOADBLOCKADDRESS TargetBlockAddress:i64<@main, %odd.i18&gt; 0
```


then I tried to match this DAG Node in TableGen:




```
def SDT_LOADBLOCKADDRESS :
SDTypeProfile<1,1,[SDTCisInt<0&gt;,SDTCisVT<1,i64&gt;]&gt;;
def _LOADBLOCKADDRESS :
SDNode<"CUSTOMISD::LOADBLOCKADDRESS",SDT_LOADBLOCKADDRESS,[SDNPHasChain]&gt;;

...
def : Pat<(i64 (_LOADBLOCKADDRESS tblockaddress:$tba)),(i64 (MOVXI8
tblockaddress:$tba))&gt;;
```


Which failed when matching opcode OPC_RecordChild1
```
unsigned ChildNo = Opcode-OPC_RecordChild0;
&nbsp; &nbsp; &nbsp; if (ChildNo &gt;= N.getNumOperands())
&nbsp; &nbsp; &nbsp; &nbsp; break; &nbsp;// Match fails if
out of range child #.

```


due to ChildNo (1) &gt;= N.getNumOperands()




Zhang
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