llvm dev - Apr 2021 - Match failed instruction selection error

Hello.
     Could you please tell me how can I solve the following problem in which I
get a
strange instruction selection error ("Match failed at index 0" - see
below for details).
     I have a shufflevector instruction that has as first operand a
MaskedGatherSDNode
whose index is (in LLVM IR):
       %5 = sext <8 x i16> %varVecIndexInnerLoop to <8 x i64>, !dbg
!24
       where
       %varVecIndexInnerLoop = phi <8 x i16> [ zeroinitializer, %vector.ph
], [
%vecIndexAddRes, %vector.body ]
     So the index of the MaskedGatherSDNode is in another basic-block.

     My problem is that I try to reuse the index in another Machine SDNode
subtract
instruction (because I want to use the same register as in the index), but then
I get the
following instruction selection error:
      Entered ConnexDAGToDAGISel::Select(): Selecting Node = t45: v8i64 =
sign_extend t44,
test.c:39:5
      Opcode = 157
      ConnexDAGToDAGISel::Select(): default case: Opcode = 157
      ISEL: Starting pattern match
        Initial Opcode index to 0
        Match failed at index 0
      LLVM ERROR: Cannot select: t45: v8i64 = sign_extend t44, test.c:39:5
        t44: v8i16,ch = CopyFromReg t0, Register:v8i16 %6, test.c:39:5
          t43: v8i16 = Register %6
      In function: Stencil


     Can I avoid this error maybe by replicating the index of the
MaskedGatherSDNode as a
separate node?

   Thank you very much,
     Alex