llvm dev - Dec 2020 - Improving the rich disassembly output

Hi,

I'm trying to use the annotation support for the LLVM disassembler, which
seems
to be implemented only on ARM and x86.

It was easy to add annotations also on SystemZ, AArch64 and MIPS (at least
<imm:> and <reg:>) and I'm going to send you soon all the
patches.

But now I'm facing a problem with the annotations in x86: there are some
instructions that emit registers directly from the AsmString written in the
TableGen file.

For example, llvm/lib/Target/X86/X86InstrInfo.td:1631, this line defines the
instruction with the `al` register hardcoded, which is emitted without markup:
```
def MOV8o32a : Ii32<0xA2, RawFrmMemOffs, (outs), (ins offset32_8:$dst),
                     "mov{b}\t{%al, $dst|$dst, al}", []>, AdSize32;
```

In this case, I tried to change "al" with "$al" (at first by
creating a new
RegisterClass "AL8" with only one register (AL) and forwarding it to
MOV8o32a)
but I got a crash while trying to emit the instruction. 
And, honestly, creating RegisterClass with only one register doesn't seem to
be
the best way to approach this problem.

For the record, the crash was:
```
Unhandled relocation encoding AL8
Unhandled relocation encoding
UNREACHABLE executed at llvm/llvm/utils/TableGen/X86RecognizableInstr.cpp:1212!
```

There are instructions like ADC64i32, ADD64i32 that emit an hardcoded register
in the generated file (something like `O << ", %rax"`) in 
build/lib/Target/X86/X86GenAsmWriter.inc but I can't find them in the any
tablegen file. 

So I'd like to ask you, can you give me some advice about how to enable
annotations for this kind of instructions?

Thanks,
Alain

I'm not sure how to add annotations to these instructions. But I can tell
you that ADC64i32 is created by the last def at the bottom of the
ArithBinOp_RF multiclass in X86InstrArithmetic.td.

~Craig

On Wed, Dec 9, 2020 at 6:10 AM Alain Carlucci via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> Hi,
>
> I'm trying to use the annotation support for the LLVM disassembler,
which
> seems
> to be implemented only on ARM and x86.
>
> It was easy to add annotations also on SystemZ, AArch64 and MIPS (at least
> <imm:> and <reg:>) and I'm going to send you soon all the
patches.
>
> But now I'm facing a problem with the annotations in x86: there are
some
> instructions that emit registers directly from the AsmString written in the
> TableGen file.
>
> For example, llvm/lib/Target/X86/X86InstrInfo.td:1631, this line defines
> the
> instruction with the `al` register hardcoded, which is emitted without
> markup:
> ```
> def MOV8o32a : Ii32<0xA2, RawFrmMemOffs, (outs), (ins offset32_8:$dst),
>                      "mov{b}\t{%al, $dst|$dst, al}", []>,
AdSize32;
> ```
>
> In this case, I tried to change "al" with "$al" (at
first by creating a new
> RegisterClass "AL8" with only one register (AL) and forwarding it
to
> MOV8o32a)
> but I got a crash while trying to emit the instruction.
> And, honestly, creating RegisterClass with only one register doesn't
seem
> to be
> the best way to approach this problem.
>
> For the record, the crash was:
> ```
> Unhandled relocation encoding AL8
> Unhandled relocation encoding
> UNREACHABLE executed at
> llvm/llvm/utils/TableGen/X86RecognizableInstr.cpp:1212!
> ```
>
> There are instructions like ADC64i32, ADD64i32 that emit an hardcoded
> register
> in the generated file (something like `O << ", %rax"`) in
> build/lib/Target/X86/X86GenAsmWriter.inc but I can't find them in the
any
> tablegen file.
>
> So I'd like to ask you, can you give me some advice about how to enable
> annotations for this kind of instructions?
>
> Thanks,
> Alain
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
> https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://lists.llvm.org/pipermail/llvm-dev/attachments/20201209/8cfd223e/attachment.html>