llvm dev - Dec 2020 - TableGen: SubTarget SchedWriteRes

Hi everyone,

I was trying to create a model for a subtarget of the ARM processors.
Though, I've been experiencing some issues. In particular, it seems like
TableGen does not consider SchedWriteRes defined in the subtarget but only
the ones defined in the ARM target.

For example, I defined a subtarget SchedWriteRes mapped onto its right
functional units for ANDri instructions but the instruction does not follow
what is defined for that SchedWriteRes, but the one defined for the
WriteALUri in the ARM target.

It may be possible that TableGen does not consider SchedWriteRes defined in
sub targets?

Regards.
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There isn't enough information in your post to be sure, but did you try
InstRW subtarget overrides in your sched description?
def : InstRW<[MyWrALU], (instregex "ANDri$")>;

________________________________
From: llvm-dev <llvm-dev-bounces at lists.llvm.org> on behalf of Pietro
D'Ettole via llvm-dev <llvm-dev at lists.llvm.org>
Sent: Wednesday, December 2, 2020 8:59 AM
To: llvm-dev at lists.llvm.org <llvm-dev at lists.llvm.org>
Subject: [llvm-dev] TableGen: SubTarget SchedWriteRes

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Hi everyone,

I was trying to create a model for a subtarget of the ARM processors. Though,
I've been experiencing some issues. In particular, it seems like TableGen
does not consider SchedWriteRes defined in the subtarget but only the ones
defined in the ARM target.

For example, I defined a subtarget SchedWriteRes mapped onto its right
functional units for ANDri instructions but the instruction does not follow what
is defined for that SchedWriteRes, but the one defined for the WriteALUri in the
ARM target.

It may be possible that TableGen does not consider SchedWriteRes defined in sub
targets?

Regards.
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