On 01/13/2016 02:45 AM, Will Deacon wrote:> On Tue, Jan 12, 2016 at 12:45:14PM -0800, Leonid Yegoshin wrote: >> > I don't think the address dependency is enough on its own. By that > reasoning, the following variant (WRC+addr+addr) would work too: > > > P0: > Wx = 1 > > P1: > Rx == 1 > <address dep> > Wy = 1 > > P2: > Ry == 1 > <address dep> > Rx = 0 > > > So are you saying that this is also forbidden? > Imagine that P0 and P1 are two threads that share a store buffer. What > then? >I ask HW team about it but I have a question - has it any relationship with replacing MIPS SYNC with lightweight SYNCs (SYNC_WMB etc)? You use any barrier or do not use it and I just voice an intention to use a more efficient instruction instead of bold hummer (SYNC instruction). If you don't use any barrier here then it is a different issue. May be it has sense to return back to original issue? - Leonid
On Wed, Jan 13, 2016 at 11:02:35AM -0800, Leonid Yegoshin wrote:> I ask HW team about it but I have a question - has it any relationship with > replacing MIPS SYNC with lightweight SYNCs (SYNC_WMB etc)?Of course. If you cannot explain the semantics of the primitives you introduce, how can we judge the patch. This barrier business is hard enough as it is, but magic unexplained hardware makes it impossible. Rest assured, you (MIPS) isn't the first (nor likely the last) to go through all this. We've had these discussions (and to a certain extend are still having them) for x86, PPC, Alpha, ARM, etc.. Any every time new barriers instructions get introduced we had better have a full and comprehensive explanation to go along with them.
On 01/13/2016 12:48 PM, Peter Zijlstra wrote:> On Wed, Jan 13, 2016 at 11:02:35AM -0800, Leonid Yegoshin wrote: > >> I ask HW team about it but I have a question - has it any relationship with >> replacing MIPS SYNC with lightweight SYNCs (SYNC_WMB etc)? > Of course. If you cannot explain the semantics of the primitives you > introduce, how can we judge the patch. > >You missed a point - it is a question about replacement of SYNC with lightweight primitives. It is NOT a question about multithread system behavior without any SYNC. The answer on a latest Will's question lies in different area. - Leonid.