llvm dev - Jun 2019 - TableGen subregister assertion

Hi all,

I'm facing a crash in TableGen (as of 7.0) when generating register info for
our out-of-tree target.

llvm-tblgen: llvm/utils/TableGen/CodeGenRegisters.cpp:128: void
llvm::CodeGenSubRegIndex::setConcatenationOf(llvm::ArrayRef<llvm::CodeGenSubRegIndex*>):
Assertion `std::equal(Parts.begin(), Parts.end(), ConcatenationOf.begin())
&& "parts consistent"' failed.

It should reproduce, even on tip, with the example RegisterInfo file I've
pasted below. Run with: llvm-tblgen -gen-register-info -I /path/to/llvm/include
TestRegInfo.td

It's something to do with SUPER1 and SUPER2 using the same index
(SubRegLo32) to index subregisters which themselves contain differently-composed
subregisters from one another: SuperQ has four quarters but I1 has two halves.

My question is: is this a documented restriction in TableGen or a bug? If
it's a design choice, should it emit a more appropriate error rather than
asserting?

Thanks,
Fraser

----------------------------------------------------------

include "llvm/Target/Target.td"

class MyReg<string name, list<Register> subregs = []>
      : RegisterWithSubRegs<name, subregs> {
  let Namespace = "TST";
}

// Quarter Registers

def Q0 : MyReg<"Q0">;
def Q1 : MyReg<"Q1">;
def Q2 : MyReg<"Q1">;
def Q3 : MyReg<"Q1">;

def SubRegQ0 : SubRegIndex<8, 0>;
def SubRegQ1 : SubRegIndex<8, 8>;
def SubRegQ2 : SubRegIndex<8, 16>;
def SubRegQ3 : SubRegIndex<8, 24>;

let SubRegIndices = [SubRegQ0, SubRegQ1,
                     SubRegQ2, SubRegQ3],
    CoveredBySubRegs = 1 in {
  def SuperQ : MyReg<"SuperQ ", [Q0, Q1, Q2, Q3]>;
}

// Half Registers

foreach i = 0-5 in {
  def H#i : MyReg<"H"#i>;
}

def SubRegLo16   : SubRegIndex<16, 0>;
def SubRegHi16   : SubRegIndex<16, 16>;

// Whole Registers

let SubRegIndices = [SubRegLo16, SubRegHi16], CoveredBySubRegs = 1 in {
  def I0 : MyReg<"I0", [H0, H1]>;
  def I1 : MyReg<"I1", [H2, H3]>;
  def I2 : MyReg<"I2", [H4, H5]>;
}

// Super Registers

def SubRegLo32 : SubRegIndex<32, 0>;
def SubRegHi32 : SubRegIndex<32, 32>;

let SubRegIndices = [SubRegLo32, SubRegHi32], CoveredBySubRegs = 1 in {
  def SUPER1 : MyReg<"SUPER1", [SuperQ, I0]>;
  def SUPER2 : MyReg<"SUPER2", [I1, I2]>;
}

def TST : Target;

class MyClass<int size, list<ValueType> types, dag registers>
      : RegisterClass<"Test", types, size, registers> {
  let Size = size;
}

def MyRegs : MyClass<32, [i32], (add I0, I1, I2)>;
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