llvm dev - Nov 2015 - Question for out of tree targets: Does tour target have a huge number of subregisters and depends on imprecise lanemasks being available?

Note: If you do not maintain an out-of-tree target with many subregister indexes
then you can stop reading now.

The current subregister liveness and register coalescing code uses lane masks to
model which parts of a register are live/covered. Lanes are modeled as bits in a
32bit unsigned int. TableGen maps subregister indexes to bits in the lane mask;
If there are more disjunct subregisters for a single register class than the
lane mask can hold then tablegen maps the remaining subregisters to the highest
bit in the lane mask, leading to a graceful degradation with imprecise
lanemasks.

These imprecise lanemasks turned out to be tricky when modeling subregister
liveness. To my knowledge the only target with that many subregister indexes
(disjunct subregisters possible for a single register class) is a single out of
tree target that we will change to use less subregister indexes. I plan to
declare lane masks as precise and change tablegen to abort if 32 bits are not
enough.

This does not affect any in tree targets, the biggest lanemasks there can be
found in AMDGPU which still fit in 16bits. If this turns out to be a problem in
the future we can easily change the typedef to use an uint64_t.

So is there an out-of-tree target that uses more subregister indexes and fails
when the attached patch is applied?

- Matthias

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