llvm dev - Feb 2014 - [LLVMdev] Possible bug with Bitcast instruction Expanding?

Hi all, 
i am using llvm-3.4 with my backend
i have those 2  .ll files  test.fp.ll
<http://llvm.1065342.n5.nabble.com/file/n66038/test.fp.ll>   and 
test.int.ll <http://llvm.1065342.n5.nabble.com/file/n66038/test.int.ll>  
.i
have v4f32 and v4i32 native types on my backend and BITCAST instruction
expanded for any type. i use llc with -O2

the code that the .ll with the v4i32 emmits is 
===============================================# BB#0:                          
# %entry
    #APP
    mov.v4 v2, v254
    #NO_APP
    st_qf   v2, v7.y, 0
    ld_qf   v2, v7.y, 0

    mov.v4  v8.x, v2.x
    addiu   v8.x, v8.x, 1
    mov.v4  v2.x, v8.x
    st_qf   v2, v7.y, 16
    ld_qf   v1, v7.y, 16

    #APP
    pixout v1, v6.y, 6
    #NO_APP
    #APP
    yield
    #NO_APP
$BB0_1:                                 # %while.body
                                        # =>This Inner Loop Header: Depth=1
    j   $BB0_1
===============================================
while the code that is emmited with the v4f32 version is 
===============================================# BB#0:                          
# %entry
    #APP
    mov.v4 v1, v254
    #NO_APP
    fset    v3.x,  1065353216

     
load/store instructions

    mov.v4  v8.x, v1.x
    add.v4  v8.x, v8.x, v3.x
    mov.v4  v1.x, v8.x

     
load/store instructions

    #APP
    pixout v1, v6.y, 6
    #NO_APP
    #APP
    yield
    #NO_APP
$BB0_1:                                 # %while.body
                                        # =>This Inner Loop Header: Depth=1
    j   $BB0_1

===============================================v4i32 and v4f32 are both in the
same Registers
def QGR128 : RegisterClass<"NemaCore",   [v4f32, v4i32 ], 128, (add
(sequence "L%u", 1, 6), (sequence "L%u", 8, 31))>;

the weird thing is that the higlight load-stores if the RegisterClass is
defined like this 

def QGR128 : RegisterClass<"NemaCore",   
[v4i32, v4f32 ],
 128, (add (sequence "L%u", 1, 6), (sequence "L%u", 8,
31))>;

they disapear from the first piece of assembly and they appear on the second
where i have highlighted.


i found that the problem is a bitcast instruction . from the one vector type
to the other. 
Is this normal?
why the way that registerclasses are defined should affect expanding ?

Thanks,
Nikos Stavropoulos
Compiler Engineer 
Think Silicon Ltd.




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i found it 

it wanted to declare BITCAST legal 
and add

  def : Pat<(v4f32  (bitconvert (v4i32 QGR128:$src))),    (v4f32
QGR128:$src)>;
  def : Pat<(v4i32  (bitconvert (v4f32 QGR128:$src))),    (v4i32
QGR128:$src)>;

on IntrsInfo.td



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