llvm dev - May 2009 - [LLVMdev] sign and zero extensions question

Hi,Could someone explain to me how the sign/zero extensions in LLVM
work, please? If I understood correctly, the int type in LLVM doesn't keep
the information about signedness of an int. So the question is how can I
know if instructions like Load or Trunc should be signed or not? I guess
that at least ARM backend  produces sign extended load so if someone could
point me to the code where it happens it would be great (I can't figure it
out).
Perhaps I should mention that I'm still working on the MSIL backend.

Thanks for your help.
Artur
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On Tue, May 26, 2009 at 6:21 AM, Artur Pietrek <pietreka at gmail.com>
wrote:
> Hi,
> Could someone explain to me how the sign/zero extensions in LLVM
> work, please? If I understood correctly, the int type in LLVM doesn't
keep
> the information about signedness of an int.
Right.
> So the question is how can I
> know if instructions like Load or Trunc should be signed or not?
If you're talking about LLVM IR instructions, neither load nor trunc
does any extension, so it doesn't matter if they are signed or not.
> I guess
> that at least ARM backend  produces sign extended load so if someone could
> point me to the code where it happens it would be great (I can't figure
it
> out).
The code generator combines a sign extension of a load into a
sign-extended load (if you're looking at the code generator, see the
definition of SEXTLOAD in include/llvm/CodeGen/SelectionDAGNodes.h).
There isn't a distinct instruction in the IR.

-Eli