llvm dev - Jan 2009 - [LLVMdev] Probably FAQ: can you insert BRCONDs during TargetLowering::LowerOperation?

It's yet another CellSPU thing: integer division is a long code  
sequence we have to insert that has branches within it (test for 0  
divisor, etc.) Can't really emit the sequence of instructions via  
tblgen (can't have labels or BBs). The other alternative is a custom  
instruction emitter.

Life could be easier if I could insert BRCONDs and other branches  
from within target-dependent lowering -- if I had access to the  
current MBB.

Is this possible or just a FAQ?


-scooter

On Jan 6, 2009, at 5:53 PM, Scott Michel wrote:
> It's yet another CellSPU thing: integer division is a long code
> sequence we have to insert that has branches within it (test for 0
> divisor, etc.) Can't really emit the sequence of instructions via
> tblgen (can't have labels or BBs). The other alternative is a custom
> instruction emitter.
>
> Life could be easier if I could insert BRCONDs and other branches
> from within target-dependent lowering -- if I had access to the
> current MBB.
>
> Is this possible or just a FAQ?
It isn't currently possible for a selection dag to represent more than  
one machine basic block.  I think Christopher Lamb had some code that  
did some of this, but I don't know how far he got.

The way we currently work around this is with a "custom scheduler  
insertion hook".  For example, see how SELECT_CC_* works on PPC: at  
isel time we claim that we have the operation, then the scheduler  
invokes a virtual function to insert it, which expands out into  
multiple MBBs.

-Chris

Chris:

I was trying to avoid using the custom instruction emitter method. Not as if
I didn't look before I asked the question to see if there was an easier way.


-scooter

On Tue, Jan 6, 2009 at 10:07 PM, Chris Lattner <clattner at apple.com>
wrote:
>
> On Jan 6, 2009, at 5:53 PM, Scott Michel wrote:
>
> > It's yet another CellSPU thing: integer division is a long code
> > sequence we have to insert that has branches within it (test for 0
> > divisor, etc.) Can't really emit the sequence of instructions via
> > tblgen (can't have labels or BBs). The other alternative is a
custom
> > instruction emitter.
> >
> > Life could be easier if I could insert BRCONDs and other branches
> > from within target-dependent lowering -- if I had access to the
> > current MBB.
> >
> > Is this possible or just a FAQ?
>
> It isn't currently possible for a selection dag to represent more than
> one machine basic block.  I think Christopher Lamb had some code that
> did some of this, but I don't know how far he got.
>
> The way we currently work around this is with a "custom scheduler
> insertion hook".  For example, see how SELECT_CC_* works on PPC: at
> isel time we claim that we have the operation, then the scheduler
> invokes a virtual function to insert it, which expands out into
> multiple MBBs.
>
> -Chris
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>
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