llvm dev - Dec 2006 - [LLVMdev] Instructions having variable names as operands

Hello.
I am Seung Jae Lee making a LLVM backend for a new architecture XCC.
I found that the instructions use variable names which actually used in the
source coding for operands unlike most architectures which use usually register
names or addresses as operands.
LLVM backend examples such as ARM, SPARC seem to use register names or addresses
for operands.
How can I implement this on my backend?
Would you mind telling me about this?
Thank you very much.

Seung Jae Lee

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Phone: +1-217-377-1932
Webpage: http://struct.nazoo.net/cv/cv_eng.htm

Graduate Research Assistant
Dept. of Civil & Environmental Engineering
University of Illinois at Urbana-Champaign
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On Thu, 14 Dec 2006, Seung Jae Lee wrote:
> I am Seung Jae Lee making a LLVM backend for a new architecture XCC. I 
> found that the instructions use variable names which actually used in 
> the source coding for operands unlike most architectures which use 
> usually register names or addresses as operands. LLVM backend examples 
> such as ARM, SPARC seem to use register names or addresses for operands. 
> How can I implement this on my backend? Would you mind telling me about 
> this? Thank you very much.
LLVM virtual register names are eliminated during code generation.  For 
example, something like this:

   %X = add int %Y, %Z

might be code generated to:

   add EAX, EBX

LLVM names are discarded very early in the code generator.  Does this help 
answer your question?  If not, can you be more specific?

-Chris

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