Use different affinity for each VCPU and always expose an SMP systems to
the guest.
Signed-off-by: Julien Grall <julien.grall@linaro.org>
---
Changes in v2:
- Create a virtual MPIDR during the VCPU initialization
---
xen/arch/arm/domain.c | 10 ++++++++--
xen/include/asm-arm/domain.h | 2 +-
xen/include/asm-arm/processor.h | 6 ++++++
3 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c
index 6937abf..bcf1755 100644
--- a/xen/arch/arm/domain.c
+++ b/xen/arch/arm/domain.c
@@ -140,7 +140,7 @@ static void ctxt_switch_to(struct vcpu *n)
isb();
WRITE_SYSREG32(n->domain->arch.vpidr, VPIDR_EL2);
- WRITE_SYSREG(n->domain->arch.vmpidr, VMPIDR_EL2);
+ WRITE_SYSREG(n->arch.vmpidr, VMPIDR_EL2);
/* VGIC */
gic_restore_state(n);
@@ -451,7 +451,14 @@ int vcpu_initialise(struct vcpu *v)
return rc;
v->arch.sctlr = SCTLR_BASE;
+ /*
+ * By default exposes an SMP system with AFFO set to the VCPU ID
+ * TODO: Handle multi-threading processor and cluster
+ */
+ v->arch.vmpidr = MPIDR_SMP | (v->vcpu_id << MPIDR_AFF0_SHIFT);
+
v->arch.actlr = READ_SYSREG32(ACTLR_EL1);
+
/* XXX: Handle other than CA15 cpus */
if ( v->domain->max_vcpus > 1 )
v->arch.actlr |= ACTLR_CA15_SMP;
@@ -490,7 +497,6 @@ int arch_domain_create(struct domain *d, unsigned int
domcr_flags)
/* Default the virtual ID to match the physical */
d->arch.vpidr = boot_cpu_data.midr.bits;
- d->arch.vmpidr = boot_cpu_data.mpidr.bits;
clear_page(d->shared_info);
share_xen_page_with_guest(
diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h
index 339b6e6..425eb71 100644
--- a/xen/include/asm-arm/domain.h
+++ b/xen/include/asm-arm/domain.h
@@ -68,7 +68,6 @@ struct arch_domain
/* Virtual CPUID */
uint32_t vpidr;
- register_t vmpidr;
struct {
uint64_t offset;
@@ -194,6 +193,7 @@ struct arch_vcpu
/* CP 15 */
uint32_t csselr;
+ uint32_t vmpidr;
uint32_t gic_hcr, gic_vmcr, gic_apr;
uint32_t gic_lr[64];
diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
index 1c9d793..5181e7b 100644
--- a/xen/include/asm-arm/processor.h
+++ b/xen/include/asm-arm/processor.h
@@ -6,6 +6,12 @@
/* MIDR Main ID Register */
#define MIDR_MASK 0xff0ffff0
+/* MPIDR Multiprocessor Affinity Register */
+#define MPIDR_UP (1 << 30)
+#define MPIDR_SMP (1 << 31)
+#define MPIDR_AFF0_SHIFT (0)
+#define MPIDR_AFF0_MASK (0xff << MPIDR_AFF0_SHIFT)
+
/* TTBCR Translation Table Base Control Register */
#define TTBCR_EAE 0x80000000
#define TTBCR_N_MASK 0x07
--
1.7.10.4
On Mon, 2013-07-15 at 15:41 +0100, Julien Grall wrote:> Use different affinity for each VCPU and always expose an SMP systems to > the guest. > > Signed-off-by: Julien Grall <julien.grall@linaro.org>Acked-by: Ian Campbell <ian.campbell@citrix.com> I would apply but it looks like it depends on your ACTLR patch, which I had a comment on.> > --- > Changes in v2: > - Create a virtual MPIDR during the VCPU initialization > --- > xen/arch/arm/domain.c | 10 ++++++++-- > xen/include/asm-arm/domain.h | 2 +- > xen/include/asm-arm/processor.h | 6 ++++++ > 3 files changed, 15 insertions(+), 3 deletions(-) > > diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c > index 6937abf..bcf1755 100644 > --- a/xen/arch/arm/domain.c > +++ b/xen/arch/arm/domain.c > @@ -140,7 +140,7 @@ static void ctxt_switch_to(struct vcpu *n) > isb(); > > WRITE_SYSREG32(n->domain->arch.vpidr, VPIDR_EL2); > - WRITE_SYSREG(n->domain->arch.vmpidr, VMPIDR_EL2); > + WRITE_SYSREG(n->arch.vmpidr, VMPIDR_EL2); > > /* VGIC */ > gic_restore_state(n); > @@ -451,7 +451,14 @@ int vcpu_initialise(struct vcpu *v) > return rc; > > v->arch.sctlr = SCTLR_BASE; > + /* > + * By default exposes an SMP system with AFFO set to the VCPU ID > + * TODO: Handle multi-threading processor and cluster > + */ > + v->arch.vmpidr = MPIDR_SMP | (v->vcpu_id << MPIDR_AFF0_SHIFT); > + > v->arch.actlr = READ_SYSREG32(ACTLR_EL1); > + > /* XXX: Handle other than CA15 cpus */ > if ( v->domain->max_vcpus > 1 ) > v->arch.actlr |= ACTLR_CA15_SMP; > @@ -490,7 +497,6 @@ int arch_domain_create(struct domain *d, unsigned int domcr_flags) > > /* Default the virtual ID to match the physical */ > d->arch.vpidr = boot_cpu_data.midr.bits; > - d->arch.vmpidr = boot_cpu_data.mpidr.bits; > > clear_page(d->shared_info); > share_xen_page_with_guest( > diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h > index 339b6e6..425eb71 100644 > --- a/xen/include/asm-arm/domain.h > +++ b/xen/include/asm-arm/domain.h > @@ -68,7 +68,6 @@ struct arch_domain > > /* Virtual CPUID */ > uint32_t vpidr; > - register_t vmpidr; > > struct { > uint64_t offset; > @@ -194,6 +193,7 @@ struct arch_vcpu > > /* CP 15 */ > uint32_t csselr; > + uint32_t vmpidr; > > uint32_t gic_hcr, gic_vmcr, gic_apr; > uint32_t gic_lr[64]; > diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h > index 1c9d793..5181e7b 100644 > --- a/xen/include/asm-arm/processor.h > +++ b/xen/include/asm-arm/processor.h > @@ -6,6 +6,12 @@ > /* MIDR Main ID Register */ > #define MIDR_MASK 0xff0ffff0 > > +/* MPIDR Multiprocessor Affinity Register */ > +#define MPIDR_UP (1 << 30) > +#define MPIDR_SMP (1 << 31) > +#define MPIDR_AFF0_SHIFT (0) > +#define MPIDR_AFF0_MASK (0xff << MPIDR_AFF0_SHIFT) > + > /* TTBCR Translation Table Base Control Register */ > #define TTBCR_EAE 0x80000000 > #define TTBCR_N_MASK 0x07
On 07/17/2013 10:55 AM, Ian Campbell wrote:> On Mon, 2013-07-15 at 15:41 +0100, Julien Grall wrote: >> Use different affinity for each VCPU and always expose an SMP systems to >> the guest. >> >> Signed-off-by: Julien Grall <julien.grall@linaro.org> > > Acked-by: Ian Campbell <ian.campbell@citrix.com> > > I would apply but it looks like it depends on your ACTLR patch, which I > had a comment on.There is no dependency between the both patch, except the "diff context". I can send a new patch.> >> >> --- >> Changes in v2: >> - Create a virtual MPIDR during the VCPU initialization >> --- >> xen/arch/arm/domain.c | 10 ++++++++-- >> xen/include/asm-arm/domain.h | 2 +- >> xen/include/asm-arm/processor.h | 6 ++++++ >> 3 files changed, 15 insertions(+), 3 deletions(-) >> >> diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c >> index 6937abf..bcf1755 100644 >> --- a/xen/arch/arm/domain.c >> +++ b/xen/arch/arm/domain.c >> @@ -140,7 +140,7 @@ static void ctxt_switch_to(struct vcpu *n) >> isb(); >> >> WRITE_SYSREG32(n->domain->arch.vpidr, VPIDR_EL2); >> - WRITE_SYSREG(n->domain->arch.vmpidr, VMPIDR_EL2); >> + WRITE_SYSREG(n->arch.vmpidr, VMPIDR_EL2); >> >> /* VGIC */ >> gic_restore_state(n); >> @@ -451,7 +451,14 @@ int vcpu_initialise(struct vcpu *v) >> return rc; >> >> v->arch.sctlr = SCTLR_BASE; >> + /* >> + * By default exposes an SMP system with AFFO set to the VCPU ID >> + * TODO: Handle multi-threading processor and cluster >> + */ >> + v->arch.vmpidr = MPIDR_SMP | (v->vcpu_id << MPIDR_AFF0_SHIFT); >> + >> v->arch.actlr = READ_SYSREG32(ACTLR_EL1); >> + >> /* XXX: Handle other than CA15 cpus */ >> if ( v->domain->max_vcpus > 1 ) >> v->arch.actlr |= ACTLR_CA15_SMP; >> @@ -490,7 +497,6 @@ int arch_domain_create(struct domain *d, unsigned int domcr_flags) >> >> /* Default the virtual ID to match the physical */ >> d->arch.vpidr = boot_cpu_data.midr.bits; >> - d->arch.vmpidr = boot_cpu_data.mpidr.bits; >> >> clear_page(d->shared_info); >> share_xen_page_with_guest( >> diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h >> index 339b6e6..425eb71 100644 >> --- a/xen/include/asm-arm/domain.h >> +++ b/xen/include/asm-arm/domain.h >> @@ -68,7 +68,6 @@ struct arch_domain >> >> /* Virtual CPUID */ >> uint32_t vpidr; >> - register_t vmpidr; >> >> struct { >> uint64_t offset; >> @@ -194,6 +193,7 @@ struct arch_vcpu >> >> /* CP 15 */ >> uint32_t csselr; >> + uint32_t vmpidr; >> >> uint32_t gic_hcr, gic_vmcr, gic_apr; >> uint32_t gic_lr[64]; >> diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h >> index 1c9d793..5181e7b 100644 >> --- a/xen/include/asm-arm/processor.h >> +++ b/xen/include/asm-arm/processor.h >> @@ -6,6 +6,12 @@ >> /* MIDR Main ID Register */ >> #define MIDR_MASK 0xff0ffff0 >> >> +/* MPIDR Multiprocessor Affinity Register */ >> +#define MPIDR_UP (1 << 30) >> +#define MPIDR_SMP (1 << 31) >> +#define MPIDR_AFF0_SHIFT (0) >> +#define MPIDR_AFF0_MASK (0xff << MPIDR_AFF0_SHIFT) >> + >> /* TTBCR Translation Table Base Control Register */ >> #define TTBCR_EAE 0x80000000 >> #define TTBCR_N_MASK 0x07 > >
On Wed, 2013-07-17 at 11:02 +0100, Julien Grall wrote:> On 07/17/2013 10:55 AM, Ian Campbell wrote: > > On Mon, 2013-07-15 at 15:41 +0100, Julien Grall wrote: > >> Use different affinity for each VCPU and always expose an SMP systems to > >> the guest. > >> > >> Signed-off-by: Julien Grall <julien.grall@linaro.org> > > > > Acked-by: Ian Campbell <ian.campbell@citrix.com> > > > > I would apply but it looks like it depends on your ACTLR patch, which I > > had a comment on. > > There is no dependency between the both patch, except the "diff context". > > I can send a new patch.Up to you if you want to respin/resend ACTLR or rebase this one in front of it.> > > > >> > >> --- > >> Changes in v2: > >> - Create a virtual MPIDR during the VCPU initialization > >> --- > >> xen/arch/arm/domain.c | 10 ++++++++-- > >> xen/include/asm-arm/domain.h | 2 +- > >> xen/include/asm-arm/processor.h | 6 ++++++ > >> 3 files changed, 15 insertions(+), 3 deletions(-) > >> > >> diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c > >> index 6937abf..bcf1755 100644 > >> --- a/xen/arch/arm/domain.c > >> +++ b/xen/arch/arm/domain.c > >> @@ -140,7 +140,7 @@ static void ctxt_switch_to(struct vcpu *n) > >> isb(); > >> > >> WRITE_SYSREG32(n->domain->arch.vpidr, VPIDR_EL2); > >> - WRITE_SYSREG(n->domain->arch.vmpidr, VMPIDR_EL2); > >> + WRITE_SYSREG(n->arch.vmpidr, VMPIDR_EL2); > >> > >> /* VGIC */ > >> gic_restore_state(n); > >> @@ -451,7 +451,14 @@ int vcpu_initialise(struct vcpu *v) > >> return rc; > >> > >> v->arch.sctlr = SCTLR_BASE; > >> + /* > >> + * By default exposes an SMP system with AFFO set to the VCPU ID > >> + * TODO: Handle multi-threading processor and cluster > >> + */ > >> + v->arch.vmpidr = MPIDR_SMP | (v->vcpu_id << MPIDR_AFF0_SHIFT); > >> + > >> v->arch.actlr = READ_SYSREG32(ACTLR_EL1); > >> + > >> /* XXX: Handle other than CA15 cpus */ > >> if ( v->domain->max_vcpus > 1 ) > >> v->arch.actlr |= ACTLR_CA15_SMP; > >> @@ -490,7 +497,6 @@ int arch_domain_create(struct domain *d, unsigned int domcr_flags) > >> > >> /* Default the virtual ID to match the physical */ > >> d->arch.vpidr = boot_cpu_data.midr.bits; > >> - d->arch.vmpidr = boot_cpu_data.mpidr.bits; > >> > >> clear_page(d->shared_info); > >> share_xen_page_with_guest( > >> diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h > >> index 339b6e6..425eb71 100644 > >> --- a/xen/include/asm-arm/domain.h > >> +++ b/xen/include/asm-arm/domain.h > >> @@ -68,7 +68,6 @@ struct arch_domain > >> > >> /* Virtual CPUID */ > >> uint32_t vpidr; > >> - register_t vmpidr; > >> > >> struct { > >> uint64_t offset; > >> @@ -194,6 +193,7 @@ struct arch_vcpu > >> > >> /* CP 15 */ > >> uint32_t csselr; > >> + uint32_t vmpidr; > >> > >> uint32_t gic_hcr, gic_vmcr, gic_apr; > >> uint32_t gic_lr[64]; > >> diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h > >> index 1c9d793..5181e7b 100644 > >> --- a/xen/include/asm-arm/processor.h > >> +++ b/xen/include/asm-arm/processor.h > >> @@ -6,6 +6,12 @@ > >> /* MIDR Main ID Register */ > >> #define MIDR_MASK 0xff0ffff0 > >> > >> +/* MPIDR Multiprocessor Affinity Register */ > >> +#define MPIDR_UP (1 << 30) > >> +#define MPIDR_SMP (1 << 31) > >> +#define MPIDR_AFF0_SHIFT (0) > >> +#define MPIDR_AFF0_MASK (0xff << MPIDR_AFF0_SHIFT) > >> + > >> /* TTBCR Translation Table Base Control Register */ > >> #define TTBCR_EAE 0x80000000 > >> #define TTBCR_N_MASK 0x07 > > > > >
On Wed, 2013-07-17 at 11:02 +0100, Julien Grall wrote:> On 07/17/2013 10:55 AM, Ian Campbell wrote: > > On Mon, 2013-07-15 at 15:41 +0100, Julien Grall wrote: > >> Use different affinity for each VCPU and always expose an SMP systems to > >> the guest. > >> > >> Signed-off-by: Julien Grall <julien.grall@linaro.org> > > > > Acked-by: Ian Campbell <ian.campbell@citrix.com> > > > > I would apply but it looks like it depends on your ACTLR patch, which I > > had a comment on. > > There is no dependency between the both patch, except the "diff context". > > I can send a new patch.I applied the ACTLR one but in the meantime I noticed an issue, I think. [...]> >> diff --git a/xen/include/asm-arm/domain.h b/xen/include/asm-arm/domain.h > >> index 339b6e6..425eb71 100644 > >> --- a/xen/include/asm-arm/domain.h > >> +++ b/xen/include/asm-arm/domain.h > >> @@ -68,7 +68,6 @@ struct arch_domain > >> > >> /* Virtual CPUID */ > >> uint32_t vpidr; > >> - register_t vmpidr; > >> > >> struct { > >> uint64_t offset; > >> @@ -194,6 +193,7 @@ struct arch_vcpu > >> > >> /* CP 15 */ > >> uint32_t csselr; > >> + uint32_t vmpidr;This register is 64-bit on arm64 so it needs to stay a register_t, which is consistent with the use of WRITE_SYSREG (as opposed to WRITE_SYSREG32). FYI the new bits are 39:32 == AFFR3 and in addition bit 31 (the MPIDR_SMP bit) is always 1 on arm64. Since you only care about AFFR0 and set SMP I don''t think your code needs to change at all. Ian.> >> > >> uint32_t gic_hcr, gic_vmcr, gic_apr; > >> uint32_t gic_lr[64]; > >> diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h > >> index 1c9d793..5181e7b 100644 > >> --- a/xen/include/asm-arm/processor.h > >> +++ b/xen/include/asm-arm/processor.h > >> @@ -6,6 +6,12 @@ > >> /* MIDR Main ID Register */ > >> #define MIDR_MASK 0xff0ffff0 > >> > >> +/* MPIDR Multiprocessor Affinity Register */ > >> +#define MPIDR_UP (1 << 30) > >> +#define MPIDR_SMP (1 << 31) > >> +#define MPIDR_AFF0_SHIFT (0) > >> +#define MPIDR_AFF0_MASK (0xff << MPIDR_AFF0_SHIFT) > >> + > >> /* TTBCR Translation Table Base Control Register */ > >> #define TTBCR_EAE 0x80000000 > >> #define TTBCR_N_MASK 0x07 > > > > >