thr3ads.net - Xen devel - [PATCH v3] Add missing Intel models to vpmu code. [Mar 2013]

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Konrad Rzeszutek Wilk

2013-Mar-05 19:59 UTC

[PATCH v3] Add missing Intel models to vpmu code.

Fixing up the vpmu code to a bit easier to read and also easier to spot
what models are what.

Please apply.

 xen/arch/x86/hvm/vmx/vpmu_core2.c | 31 +++++++++++++++++++++----------
 1 file changed, 21 insertions(+), 10 deletions(-)


Konrad Rzeszutek Wilk (3):
      x86/Intel: Provide comments for which model is what.
      x86/Intel: Add missing Merom, Westmere, and Nehelem models.
      x86/intel: change models number from decimal to hex.

Konrad Rzeszutek Wilk

2013-Mar-05 19:59 UTC

head link

[PATCH 1/3] x86/Intel: Provide comments for which model is what.

Acked-by: Tim Deegan <tim@xen.org>
[v1: Tim suggested to remove ''current'' from the comments]
[v2: Simon Rowe spotted Romley being spelled incorrectly]
Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
---
 xen/arch/x86/hvm/vmx/vpmu_core2.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/xen/arch/x86/hvm/vmx/vpmu_core2.c
b/xen/arch/x86/hvm/vmx/vpmu_core2.c
index 2cef2d6..4d33231 100644
--- a/xen/arch/x86/hvm/vmx/vpmu_core2.c
+++ b/xen/arch/x86/hvm/vmx/vpmu_core2.c
@@ -738,16 +738,16 @@ int vmx_vpmu_initialise(struct vcpu *v, unsigned int
vpmu_flags)
     {
         switch ( cpu_model )
         {
-        case 15:
-        case 23:
-        case 26:
-        case 29:
-        case 42:
-        case 45:
-        case 46:
-        case 47:
-        case 58:
-        case 62:
+        case 15: /* original 65 nm celeron/pentium/core2/xeon,
"Merom"/"Conroe" */
+        case 23: /* 45 nm celeron/core2/xeon
"Penryn"/"Wolfdale" */
+        case 26: /* 45 nm nehalem, "Bloomfield" */
+        case 29: /* six-core 45 nm xeon "Dunnington" */
+        case 42: /* SandyBridge */
+        case 45: /* SandyBridge, "Romley-EP" */
+        case 46: /* 45 nm nehalem-ex, "Beckton" */
+        case 47: /* 32 nm Xeon E7 */
+        case 58: /* IvyBridge */
+        case 62: /* IvyBridge EP */
             ret = core2_vpmu_initialise(v, vpmu_flags);
             if ( !ret )
                 vpmu->arch_vpmu_ops = &core2_vpmu_ops;
-- 
1.8.0.2

Konrad Rzeszutek Wilk

2013-Mar-05 19:59 UTC

head link

[PATCH 2/3] x86/Intel: Add missing Merom, Westmere, and Nehelem models.

Mainly 22 (Merom-L); 30 (Nehelem); and 37, 44 (Westmere).

A comprehensive list is available at:
http://software.intel.com/en-us/articles/intel-architecture-and-processor-identification-with-cpuid-model-and-family-numbers

[v1: Rebased]
[v2: Per Jun Nakajima comments fixed the description].
Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
---
 xen/arch/x86/hvm/vmx/vpmu_core2.c | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/xen/arch/x86/hvm/vmx/vpmu_core2.c
b/xen/arch/x86/hvm/vmx/vpmu_core2.c
index 4d33231..eb595cd 100644
--- a/xen/arch/x86/hvm/vmx/vpmu_core2.c
+++ b/xen/arch/x86/hvm/vmx/vpmu_core2.c
@@ -738,14 +738,25 @@ int vmx_vpmu_initialise(struct vcpu *v, unsigned int
vpmu_flags)
     {
         switch ( cpu_model )
         {
+        /* Core2: */
         case 15: /* original 65 nm celeron/pentium/core2/xeon,
"Merom"/"Conroe" */
+        case 22: /* single-core 65 nm celeron/core2solo
"Merom-L"/"Conroe-L" */
         case 23: /* 45 nm celeron/core2/xeon
"Penryn"/"Wolfdale" */
-        case 26: /* 45 nm nehalem, "Bloomfield" */
         case 29: /* six-core 45 nm xeon "Dunnington" */
+
         case 42: /* SandyBridge */
         case 45: /* SandyBridge, "Romley-EP" */
+
+        /* Nehalem: */
+        case 26: /* 45 nm nehalem, "Bloomfield" */
+        case 30: /* 45 nm nehalem, "Lynnfield",
"Clarksfield", "Jasper Forest" */
         case 46: /* 45 nm nehalem-ex, "Beckton" */
-        case 47: /* 32 nm Xeon E7 */
+
+        /* Westmere: */
+        case 37: /* 32 nm nehalem, "Clarkdale", "Arrandale"
*/
+        case 44: /* 32 nm nehalem, "Gulftown",
"Westmere-EP" */
+        case 47: /* 32 nm Westmere-EX */
+
         case 58: /* IvyBridge */
         case 62: /* IvyBridge EP */
             ret = core2_vpmu_initialise(v, vpmu_flags);
-- 
1.8.0.2

Konrad Rzeszutek Wilk

2013-Mar-05 19:59 UTC

head link

[PATCH 3/3] x86/intel: change models number from decimal to hex.

Suggested-by: "Nakajima, Jun" <jun.nakajima@intel.com>
Suggested-by: Jan Beulich <JBeulich@suse.com>
Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
---
 xen/arch/x86/hvm/vmx/vpmu_core2.c | 28 ++++++++++++++--------------
 1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/xen/arch/x86/hvm/vmx/vpmu_core2.c
b/xen/arch/x86/hvm/vmx/vpmu_core2.c
index eb595cd..2af8966 100644
--- a/xen/arch/x86/hvm/vmx/vpmu_core2.c
+++ b/xen/arch/x86/hvm/vmx/vpmu_core2.c
@@ -739,26 +739,26 @@ int vmx_vpmu_initialise(struct vcpu *v, unsigned int
vpmu_flags)
         switch ( cpu_model )
         {
         /* Core2: */
-        case 15: /* original 65 nm celeron/pentium/core2/xeon,
"Merom"/"Conroe" */
-        case 22: /* single-core 65 nm celeron/core2solo
"Merom-L"/"Conroe-L" */
-        case 23: /* 45 nm celeron/core2/xeon
"Penryn"/"Wolfdale" */
-        case 29: /* six-core 45 nm xeon "Dunnington" */
+        case 0x0f: /* original 65 nm celeron/pentium/core2/xeon,
"Merom"/"Conroe" */
+        case 0x16: /* single-core 65 nm celeron/core2solo
"Merom-L"/"Conroe-L" */
+        case 0x17: /* 45 nm celeron/core2/xeon
"Penryn"/"Wolfdale" */
+        case 0x1d: /* six-core 45 nm xeon "Dunnington" */
 
-        case 42: /* SandyBridge */
-        case 45: /* SandyBridge, "Romley-EP" */
+        case 0x2a: /* SandyBridge */
+        case 0x2d: /* SandyBridge, "Romley-EP" */
 
         /* Nehalem: */
-        case 26: /* 45 nm nehalem, "Bloomfield" */
-        case 30: /* 45 nm nehalem, "Lynnfield",
"Clarksfield", "Jasper Forest" */
-        case 46: /* 45 nm nehalem-ex, "Beckton" */
+        case 0x1a: /* 45 nm nehalem, "Bloomfield" */
+        case 0x1e: /* 45 nm nehalem, "Lynnfield",
"Clarksfield", "Jasper Forest" */
+        case 0x2e: /* 45 nm nehalem-ex, "Beckton" */
 
         /* Westmere: */
-        case 37: /* 32 nm nehalem, "Clarkdale", "Arrandale"
*/
-        case 44: /* 32 nm nehalem, "Gulftown",
"Westmere-EP" */
-        case 47: /* 32 nm Westmere-EX */
+        case 0x25: /* 32 nm nehalem, "Clarkdale",
"Arrandale" */
+        case 0x2c: /* 32 nm nehalem, "Gulftown",
"Westmere-EP" */
+        case 0x27: /* 32 nm Westmere-EX */
 
-        case 58: /* IvyBridge */
-        case 62: /* IvyBridge EP */
+        case 0x3a: /* IvyBridge */
+        case 0x3e: /* IvyBridge EP */
             ret = core2_vpmu_initialise(v, vpmu_flags);
             if ( !ret )
                 vpmu->arch_vpmu_ops = &core2_vpmu_ops;
-- 
1.8.0.2

Jan Beulich

2013-Mar-08 08:49 UTC

head link

Re: [PATCH 2/3] x86/Intel: Add missing Merom, Westmere, and Nehelem models.

>>> On 05.03.13 at 20:59, Konrad Rzeszutek Wilk
<konrad.wilk@oracle.com> wrote:
> Mainly 22 (Merom-L); 30 (Nehelem); and 37, 44 (Westmere).
> 
> A comprehensive list is available at:
>
http://software.intel.com/en-us/articles/intel-architecture-and-processor-identif
> ication-with-cpuid-model-and-family-numbers
> 
> [v1: Rebased]
> [v2: Per Jun Nakajima comments fixed the description].
> Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Jun, care to ack (or have someone at Intel ack) this?

Thanks, Jan
> ---
>  xen/arch/x86/hvm/vmx/vpmu_core2.c | 15 +++++++++++++--
>  1 file changed, 13 insertions(+), 2 deletions(-)
> 
> diff --git a/xen/arch/x86/hvm/vmx/vpmu_core2.c 
> b/xen/arch/x86/hvm/vmx/vpmu_core2.c
> index 4d33231..eb595cd 100644
> --- a/xen/arch/x86/hvm/vmx/vpmu_core2.c
> +++ b/xen/arch/x86/hvm/vmx/vpmu_core2.c
> @@ -738,14 +738,25 @@ int vmx_vpmu_initialise(struct vcpu *v, unsigned int 
> vpmu_flags)
>      {
>          switch ( cpu_model )
>          {
> +        /* Core2: */
>          case 15: /* original 65 nm celeron/pentium/core2/xeon, 
> "Merom"/"Conroe" */
> +        case 22: /* single-core 65 nm celeron/core2solo
"Merom-L"/"Conroe-L"
> */
>          case 23: /* 45 nm celeron/core2/xeon
"Penryn"/"Wolfdale" */
> -        case 26: /* 45 nm nehalem, "Bloomfield" */
>          case 29: /* six-core 45 nm xeon "Dunnington" */
> +
>          case 42: /* SandyBridge */
>          case 45: /* SandyBridge, "Romley-EP" */
> +
> +        /* Nehalem: */
> +        case 26: /* 45 nm nehalem, "Bloomfield" */
> +        case 30: /* 45 nm nehalem, "Lynnfield",
"Clarksfield", "Jasper
> Forest" */
>          case 46: /* 45 nm nehalem-ex, "Beckton" */
> -        case 47: /* 32 nm Xeon E7 */
> +
> +        /* Westmere: */
> +        case 37: /* 32 nm nehalem, "Clarkdale",
"Arrandale" */
> +        case 44: /* 32 nm nehalem, "Gulftown",
"Westmere-EP" */
> +        case 47: /* 32 nm Westmere-EX */
> +
>          case 58: /* IvyBridge */
>          case 62: /* IvyBridge EP */
>              ret = core2_vpmu_initialise(v, vpmu_flags);
> -- 
> 1.8.0.2

Nakajima, Jun

2013-Mar-08 14:46 UTC

head link

Re: [PATCH 2/3] x86/Intel: Add missing Merom, Westmere, and Nehelem models.

On Fri, Mar 8, 2013 at 12:49 AM, Jan Beulich <JBeulich@suse.com>
wrote:>
> >>> On 05.03.13 at 20:59, Konrad Rzeszutek Wilk
<konrad.wilk@oracle.com>
> >>> wrote:
> > Mainly 22 (Merom-L); 30 (Nehelem); and 37, 44 (Westmere).
> >
> > A comprehensive list is available at:
> >
> >
http://software.intel.com/en-us/articles/intel-architecture-and-processor-identif
> > ication-with-cpuid-model-and-family-numbers
> >
> > [v1: Rebased]
> > [v2: Per Jun Nakajima comments fixed the description].
> > Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
>
> Jun, care to ack (or have someone at Intel ack) this?
>
Acked-by: Jun Nakajima <jun.nakajima@intel.com>

--
Jun
Intel Open Source Technology Center

Xen devel - Mar 2013 - [PATCH v3] Add missing Intel models to vpmu code.

[PATCH v3] Add missing Intel models to vpmu code.

[PATCH 1/3] x86/Intel: Provide comments for which model is what.

[PATCH 2/3] x86/Intel: Add missing Merom, Westmere, and Nehelem models.

[PATCH 3/3] x86/intel: change models number from decimal to hex.

Re: [PATCH 2/3] x86/Intel: Add missing Merom, Westmere, and Nehelem models.

Re: [PATCH 2/3] x86/Intel: Add missing Merom, Westmere, and Nehelem models.