In vlapic_set_irq, we set the IRR register before the TMR. And the IRR might be
serviced before setting TMR, and even worse EOI might occur before TMR setting,
in which case the vioapic_update_EOI won''t be called, and further
prevent all the subsequent interrupt injecting. Reorder setting the TMR and IRR
will solve the problem. Besides, KVM has fixed a similar bug in:
http://markmail.org/search/?q=APIC_TMR#query:APIC_TMR+page:1+mid:rphs4f7lkxjlldne+state:results
Signed-off-by: Yongan Liu<Liuyongan@huawei.com>
diff -r cfe28865e513 xen-4.1.2/xen/arch/x86/hvm/vlapic.c
--- a/xen-4.1.2/xen/arch/x86/hvm/vlapic.c Wed Jan 04 18:50:58 2012 +0800
+++ b/xen-4.1.2/xen/arch/x86/hvm/vlapic.c Wed Jan 04 18:53:50 2012 +0800
@@ -144,10 +144,11 @@
{
int ret;
- ret = !vlapic_test_and_set_irr(vec, vlapic);
if ( trig )
vlapic_set_vector(vec, &vlapic->regs->data[APIC_TMR]);
+ ret = !vlapic_test_and_set_irr(vec, vlapic);
+
/* We may need to wake up target vcpu, besides set pending bit here */
return ret;
}
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