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Jan Beulich

2011-Oct-04 11:32 UTC

[Xen-devel] [PATCH] VMX: extend last branch MSR info to cover newer CPU models

There are still a couple of family 6 models missing here: 37, 44, 46,
and 47 (according to SDM doc changes May 2011); presumably they would
all go into the Nehalem/Sandy Bridge group. Intel?

Signed-off-by: Jan Beulich <jbeulich@suse.com>

--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -1693,6 +1693,20 @@ static const struct lbr_info {
     { MSR_C2_LASTBRANCH_0_FROM_IP,  NUM_MSR_C2_LASTBRANCH_FROM_TO },
     { MSR_C2_LASTBRANCH_0_TO_IP,    NUM_MSR_C2_LASTBRANCH_FROM_TO },
     { 0, 0 }
+}, nh_lbr[] = {
+    { MSR_IA32_LASTINTFROMIP,       1 },
+    { MSR_IA32_LASTINTTOIP,         1 },
+    { MSR_C2_LASTBRANCH_TOS,        1 },
+    { MSR_P4_LASTBRANCH_0_FROM_LIP, NUM_MSR_P4_LASTBRANCH_FROM_TO },
+    { MSR_P4_LASTBRANCH_0_TO_LIP,   NUM_MSR_P4_LASTBRANCH_FROM_TO },
+    { 0, 0 }
+}, at_lbr[] = {
+    { MSR_IA32_LASTINTFROMIP,       1 },
+    { MSR_IA32_LASTINTTOIP,         1 },
+    { MSR_C2_LASTBRANCH_TOS,        1 },
+    { MSR_C2_LASTBRANCH_0_FROM_IP,  NUM_MSR_ATOM_LASTBRANCH_FROM_TO },
+    { MSR_C2_LASTBRANCH_0_TO_IP,    NUM_MSR_ATOM_LASTBRANCH_FROM_TO },
+    { 0, 0 }
 #ifdef __i386__
 }, pm_lbr[] = {
     { MSR_IA32_LASTINTFROMIP,       1 },
@@ -1720,8 +1734,20 @@ static const struct lbr_info *last_branc
 #endif
         /* Core2 Duo */
         case 15:
+        /* Enhanced Core */
+        case 23:
             return c2_lbr;
             break;
+        /* Nehalem */
+        case 26: case 30: case 31: case 46:
+        /* Sandy Bridge */
+        case 42: case 45:
+            return nh_lbr;
+            break;
+        /* Atom */
+        case 28:
+            return at_lbr;
+            break;
         }
         break;
 
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -472,11 +472,12 @@
 #define MSR_PM_LASTBRANCH_0		0x00000040
 #define NUM_MSR_PM_LASTBRANCH		8
 
-/* Core 2 last-branch recording */
+/* Core 2 and Atom last-branch recording */
 #define MSR_C2_LASTBRANCH_TOS		0x000001c9
 #define MSR_C2_LASTBRANCH_0_FROM_IP	0x00000040
 #define MSR_C2_LASTBRANCH_0_TO_IP	0x00000060
 #define NUM_MSR_C2_LASTBRANCH_FROM_TO	4
+#define NUM_MSR_ATOM_LASTBRANCH_FROM_TO	8
 
 /* Intel Core-based CPU performance counters */
 #define MSR_CORE_PERF_FIXED_CTR0	0x00000309




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Keir Fraser

2011-Oct-04 12:00 UTC

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Re: [Xen-devel] [PATCH] VMX: extend last branch MSR info to cover newer CPU models

On 04/10/2011 12:32, "Jan Beulich" <JBeulich@suse.com> wrote:
> There are still a couple of family 6 models missing here: 37, 44, 46,
> and 47 (according to SDM doc changes May 2011); presumably they would
> all go into the Nehalem/Sandy Bridge group. Intel?
> 
> Signed-off-by: Jan Beulich <jbeulich@suse.com>
A nod or Ack from someone at Intel would be nice for this patch.

 -- Keir
> --- a/xen/arch/x86/hvm/vmx/vmx.c
> +++ b/xen/arch/x86/hvm/vmx/vmx.c
> @@ -1693,6 +1693,20 @@ static const struct lbr_info {
>      { MSR_C2_LASTBRANCH_0_FROM_IP,  NUM_MSR_C2_LASTBRANCH_FROM_TO },
>      { MSR_C2_LASTBRANCH_0_TO_IP,    NUM_MSR_C2_LASTBRANCH_FROM_TO },
>      { 0, 0 }
> +}, nh_lbr[] = {
> +    { MSR_IA32_LASTINTFROMIP,       1 },
> +    { MSR_IA32_LASTINTTOIP,         1 },
> +    { MSR_C2_LASTBRANCH_TOS,        1 },
> +    { MSR_P4_LASTBRANCH_0_FROM_LIP, NUM_MSR_P4_LASTBRANCH_FROM_TO },
> +    { MSR_P4_LASTBRANCH_0_TO_LIP,   NUM_MSR_P4_LASTBRANCH_FROM_TO },
> +    { 0, 0 }
> +}, at_lbr[] = {
> +    { MSR_IA32_LASTINTFROMIP,       1 },
> +    { MSR_IA32_LASTINTTOIP,         1 },
> +    { MSR_C2_LASTBRANCH_TOS,        1 },
> +    { MSR_C2_LASTBRANCH_0_FROM_IP,  NUM_MSR_ATOM_LASTBRANCH_FROM_TO },
> +    { MSR_C2_LASTBRANCH_0_TO_IP,    NUM_MSR_ATOM_LASTBRANCH_FROM_TO },
> +    { 0, 0 }
>  #ifdef __i386__
>  }, pm_lbr[] = {
>      { MSR_IA32_LASTINTFROMIP,       1 },
> @@ -1720,8 +1734,20 @@ static const struct lbr_info *last_branc
>  #endif
>          /* Core2 Duo */
>          case 15:
> +        /* Enhanced Core */
> +        case 23:
>              return c2_lbr;
>              break;
> +        /* Nehalem */
> +        case 26: case 30: case 31: case 46:
> +        /* Sandy Bridge */
> +        case 42: case 45:
> +            return nh_lbr;
> +            break;
> +        /* Atom */
> +        case 28:
> +            return at_lbr;
> +            break;
>          }
>          break;
>  
> --- a/xen/include/asm-x86/msr-index.h
> +++ b/xen/include/asm-x86/msr-index.h
> @@ -472,11 +472,12 @@
>  #define MSR_PM_LASTBRANCH_0  0x00000040
>  #define NUM_MSR_PM_LASTBRANCH  8
>  
> -/* Core 2 last-branch recording */
> +/* Core 2 and Atom last-branch recording */
>  #define MSR_C2_LASTBRANCH_TOS  0x000001c9
>  #define MSR_C2_LASTBRANCH_0_FROM_IP 0x00000040
>  #define MSR_C2_LASTBRANCH_0_TO_IP 0x00000060
>  #define NUM_MSR_C2_LASTBRANCH_FROM_TO 4
> +#define NUM_MSR_ATOM_LASTBRANCH_FROM_TO 8
>  
>  /* Intel Core-based CPU performance counters */
>  #define MSR_CORE_PERF_FIXED_CTR0 0x00000309
> 
> 
> 
> 
> _______________________________________________
> Xen-devel mailing list
> Xen-devel@lists.xensource.com
> http://lists.xensource.com/xen-devel


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Haitao Shan

2011-Oct-13 07:58 UTC

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Re: [Xen-devel] [PATCH] VMX: extend last branch MSR info to cover newer CPU models

Hi, Keir, Jan,

I will ACK to Jan''s patch.
Concernng Jan''s question, I am not sure whether the specific model is
NHM or SNB. But I can confirm they are all NHM/SNB. I think this is
not important to last branch record, though.

Shan Haitao

2011/10/4 Keir Fraser <keir@xen.org>:> On 04/10/2011 12:32, "Jan Beulich" <JBeulich@suse.com>
wrote:
>
>> There are still a couple of family 6 models missing here: 37, 44, 46,
>> and 47 (according to SDM doc changes May 2011); presumably they would
>> all go into the Nehalem/Sandy Bridge group. Intel?
>>
>> Signed-off-by: Jan Beulich <jbeulich@suse.com>
>
> A nod or Ack from someone at Intel would be nice for this patch.
>
>  -- Keir
>
>> --- a/xen/arch/x86/hvm/vmx/vmx.c
>> +++ b/xen/arch/x86/hvm/vmx/vmx.c
>> @@ -1693,6 +1693,20 @@ static const struct lbr_info {
>>      { MSR_C2_LASTBRANCH_0_FROM_IP,  NUM_MSR_C2_LASTBRANCH_FROM_TO },
>>      { MSR_C2_LASTBRANCH_0_TO_IP,    NUM_MSR_C2_LASTBRANCH_FROM_TO },
>>      { 0, 0 }
>> +}, nh_lbr[] = {
>> +    { MSR_IA32_LASTINTFROMIP,       1 },
>> +    { MSR_IA32_LASTINTTOIP,         1 },
>> +    { MSR_C2_LASTBRANCH_TOS,        1 },
>> +    { MSR_P4_LASTBRANCH_0_FROM_LIP, NUM_MSR_P4_LASTBRANCH_FROM_TO },
>> +    { MSR_P4_LASTBRANCH_0_TO_LIP,   NUM_MSR_P4_LASTBRANCH_FROM_TO },
>> +    { 0, 0 }
>> +}, at_lbr[] = {
>> +    { MSR_IA32_LASTINTFROMIP,       1 },
>> +    { MSR_IA32_LASTINTTOIP,         1 },
>> +    { MSR_C2_LASTBRANCH_TOS,        1 },
>> +    { MSR_C2_LASTBRANCH_0_FROM_IP,  NUM_MSR_ATOM_LASTBRANCH_FROM_TO },
>> +    { MSR_C2_LASTBRANCH_0_TO_IP,    NUM_MSR_ATOM_LASTBRANCH_FROM_TO },
>> +    { 0, 0 }
>>  #ifdef __i386__
>>  }, pm_lbr[] = {
>>      { MSR_IA32_LASTINTFROMIP,       1 },
>> @@ -1720,8 +1734,20 @@ static const struct lbr_info *last_branc
>>  #endif
>>          /* Core2 Duo */
>>          case 15:
>> +        /* Enhanced Core */
>> +        case 23:
>>              return c2_lbr;
>>              break;
>> +        /* Nehalem */
>> +        case 26: case 30: case 31: case 46:
>> +        /* Sandy Bridge */
>> +        case 42: case 45:
>> +            return nh_lbr;
>> +            break;
>> +        /* Atom */
>> +        case 28:
>> +            return at_lbr;
>> +            break;
>>          }
>>          break;
>>
>> --- a/xen/include/asm-x86/msr-index.h
>> +++ b/xen/include/asm-x86/msr-index.h
>> @@ -472,11 +472,12 @@
>>  #define MSR_PM_LASTBRANCH_0  0x00000040
>>  #define NUM_MSR_PM_LASTBRANCH  8
>>
>> -/* Core 2 last-branch recording */
>> +/* Core 2 and Atom last-branch recording */
>>  #define MSR_C2_LASTBRANCH_TOS  0x000001c9
>>  #define MSR_C2_LASTBRANCH_0_FROM_IP 0x00000040
>>  #define MSR_C2_LASTBRANCH_0_TO_IP 0x00000060
>>  #define NUM_MSR_C2_LASTBRANCH_FROM_TO 4
>> +#define NUM_MSR_ATOM_LASTBRANCH_FROM_TO 8
>>
>>  /* Intel Core-based CPU performance counters */
>>  #define MSR_CORE_PERF_FIXED_CTR0 0x00000309
>>
>>
>>
>>
>> _______________________________________________
>> Xen-devel mailing list
>> Xen-devel@lists.xensource.com
>> http://lists.xensource.com/xen-devel
>
>
>
> _______________________________________________
> Xen-devel mailing list
> Xen-devel@lists.xensource.com
> http://lists.xensource.com/xen-devel
>
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Jan Beulich

2011-Oct-13 08:18 UTC

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Re: [Xen-devel] [PATCH] VMX: extend last branch MSR info to cover newer CPU models

>>> On 13.10.11 at 09:58, Haitao Shan <maillists.shan@gmail.com>
wrote:
> Concernng Jan''s question, I am not sure whether the specific model
is
> NHM or SNB. But I can confirm they are all NHM/SNB. I think this is
> not important to last branch record, though.
So this would be the follow-up patch then:

VMX: extend last branch MSR info to cover newer CPU models #2

Signed-off-by: Jan Beulich <jbeulich@suse.com>

--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -1738,10 +1738,9 @@ static const struct lbr_info *last_branc
         case 23:
             return c2_lbr;
             break;
-        /* Nehalem */
-        case 26: case 30: case 31: case 46:
-        /* Sandy Bridge */
-        case 42: case 45:
+        /* Nehalem/Sandy Bridge */
+        case 26: case 30: case 31: case 37:
+        case 42: case 44: case 45: case 46: case 47:
             return nh_lbr;
             break;
         /* Atom */




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Xen devel - Oct 2011 - [PATCH] VMX: extend last branch MSR info to cover newer CPU models

[Xen-devel] [PATCH] VMX: extend last branch MSR info to cover newer CPU models

Re: [Xen-devel] [PATCH] VMX: extend last branch MSR info to cover newer CPU models

Re: [Xen-devel] [PATCH] VMX: extend last branch MSR info to cover newer CPU models

Re: [Xen-devel] [PATCH] VMX: extend last branch MSR info to cover newer CPU models