similar to: how to modify the histogram's frequencies

Displaying 20 results from an estimated 4000 matches similar to: "how to modify the histogram's frequencies"

2006 Jul 07
1
replace values in data frame
Hi all, I have a three columned list that I have imported into R. The first column is a plot (ex. Plot1), the second is a species name (ex ACERRUB) and the third a numeric value. I want to replace some of the second column names with other names (for example replace ACERRUB with ACERDRU). The original and replacement values are in separate lists (not vectors), but I can't seem to find the
2008 Feb 05
2
help with oop in R - class structure and syntex
Hi, I read section 5, oop, of the R lang doc, and I am still not sure I understand how to build a class in R for oop. I thought that since I understand the oop syntex of Java and VB, I am wondering if the R programmig experts could help me out by comparing and contrasting the oop syntex in R with that of Java. For example, the basic class structure in Java is like this: public class Bicycle {
2012 Feb 03
2
[LLVMdev] How to properly use copyValue?
Since there are no constructors for Value, how do you properly insert a new Value? If I create a pointer Value *newValue and then call AA.copyValue(oldValue, newValue), this does not work, since newValue is not allocated. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20120203/44086cf5/attachment.html>
2015 Apr 30
2
búsqueda y sustitución masiva
Hola a tod en s, explico lo que estoy intentando hacer... Tengo un listado de url comprimidas de twitter, entre las cuales hay muchas repetidas, por lo que el número de registros llega a más de 15K. Por otro lado tengo otra lista de esas url únicas con su equivalente ya descomprimido llegando a un registro de 900. El problema que tengo es que estoy intentando hacer un loop para hacer la
2013 May 07
6
[LLVMdev] Predicated Vector Operations
I'm trying to understand how predicated/masked instructions can be generated in llvm, specifically an instruction where a set bit in the mask will write the new result into the corresponding vector lane in the destination and a clear bit will cause the lane in the destination to remain what it was before the instruction executed. I've seen a few places that suggest 'select' is the
2012 Feb 04
0
[LLVMdev] How to properly use copyValue?
Ryan Taylor wrote: > Since there are no constructors for Value, how do you properly insert a > new Value? Value is a pure base. If you want to construct a new Value, then you want to construct a global variable or instruction or argument or something in particular. > If I create a pointer Value *newValue and then call > AA.copyValue(oldValue, newValue), this does not work, since
2012 Feb 05
1
[LLVMdev] How to properly use copyValue?
Nick, First, thanks for responding. Secondly, I just want to create an exact copy of an already exisitng Value, this should be pretty simple to do but I'm unclear on how to do this? For example, PHINode::getIncomingValue (unsigned) returns a "Value" and I want to make a copy of that Value. Is there some other way to do this other than copyValue() that I'm missing? On Sat,
2011 Apr 05
1
question about assignment warnings for replacement methods
Hi, I have seen several packages that with the most recent version of R are giving a warning like this: Assignments in \usage in documentation object 'marginalData-methods': marginalData(object) = value I assume that this is to prevent people from making assignments in their usage statements (which seems completely understandable). But what about the case above? This is a person
2013 May 08
0
[LLVMdev] Predicated Vector Operations
Jeff Bush <jeffbush001 at gmail.com> writes: > I'm trying to understand how predicated/masked instructions can be > generated in llvm, specifically an instruction where a set bit in the > mask will write the new result into the corresponding vector lane in > the destination and a clear bit will cause the lane in the destination > to remain what it was before the
2007 Oct 06
1
override variables
Hi, I am trying to allow certain nodes to override variables in inherited classes. Here''s an example: node ''my.server.com'' inherits webserver {} node ''other.server.com'' inherits webserver { $var = "newvalue" } node webserver { $var = "value" include snmp, dns, classx } In this example classx ends up using
2012 Aug 16
3
[LLVMdev] error: instruction requires: thumb2
Hi Everybody, I recently did a cross-compiling using clang (built with host=x86, target=arm) with the following command: > clang -march=armv7-a -mfloat-abi=soft -ccc-host-triple arm-none-linux-gnueabi -integrated-as main.c -o main.o -c and get error message: ------------------------------------------------------- main.c:9:9: error: instruction requires: thumb2 "ldrex
2013 May 10
0
[LLVMdev] Predicated Vector Operations
On May 10, 2013, at 11:53 AM, dag at cray.com wrote: > Jeff Bush <jeffbush001 at gmail.com> writes: > >> Ah, I think I get it now. This was mentioned earlier in the thread, >> but it didn't click at the time. It sounds like I can do instruction >> selection with a pattern like (omitting selection of the sources): >> >> let Constraints = "$dst
2013 May 09
0
[LLVMdev] Predicated Vector Operations
On Thu, May 9, 2013 at 8:10 AM, <dag at cray.com> wrote: > Jeff Bush <jeffbush001 at gmail.com> writes: > >> %tx = select %mask, %x, <0.0, 0.0, 0.0 ...> >> %ty = select %mask, %y, <0.0, 0.0, 0.0 ...> >> %sum = fadd %tx, %ty >> %newvalue = select %mask, %sum, %oldvalue >> >> I believe the generated instructions depend on whether
2013 May 10
4
[LLVMdev] Predicated Vector Operations
Jeff Bush <jeffbush001 at gmail.com> writes: > Ah, I think I get it now. This was mentioned earlier in the thread, > but it didn't click at the time. It sounds like I can do instruction > selection with a pattern like (omitting selection of the sources): > > let Constraints = "$dst = $oldvalue" in { > def MASKEDARITH : MyInstruction< >
2013 May 09
2
[LLVMdev] Predicated Vector Operations
On May 9, 2013, at 3:05 PM, Jeff Bush <jeffbush001 at gmail.com> wrote: > On Thu, May 9, 2013 at 8:10 AM, <dag at cray.com> wrote: >> Jeff Bush <jeffbush001 at gmail.com> writes: >> >>> %tx = select %mask, %x, <0.0, 0.0, 0.0 ...> >>> %ty = select %mask, %y, <0.0, 0.0, 0.0 ...> >>> %sum = fadd %tx, %ty >>> %newvalue
2012 Aug 16
0
[LLVMdev] error: instruction requires: thumb2
On Thu, Aug 16, 2012 at 12:55 PM, Lei Zhao <leizhao833 at gmail.com> wrote: > Hi Everybody, > > I recently did a cross-compiling using clang (built with host=x86, target=arm) with the following command: > > > clang -march=armv7-a -mfloat-abi=soft -ccc-host-triple arm-none-linux-gnueabi -integrated-as main.c -o main.o -c > > and get error message: > >
2016 Jun 28
3
Question about changes to 'SelectionDAGISel.h'
It occurred to me that instead of the various breakout 'Select*' functions returning the 'SDNode*' result, maybe I should be calling: ReplaceNode(N, newValue); return; or: SelectCode(N); return; Perhaps? MartinO From: Martin J. O'Riordan [mailto:martin.oriordan at movidius.com] Sent: 28 June 2016 16:49 To: 'LLVM Developers'
2012 Aug 16
2
[LLVMdev] error: instruction requires: thumb2
It works. But a follow-up question: why do I have to compile it to thumb mode in order to pass the compilation? Is there a way to make it compile to regular arm mode? Thanks. - Lei On Aug 16, 2012, at 4:00 PM, Eli Friedman wrote: > On Thu, Aug 16, 2012 at 12:55 PM, Lei Zhao <leizhao833 at gmail.com> wrote: >> Hi Everybody, >> >> I recently did a cross-compiling
2013 Jan 18
0
[LLVMdev] simple optimization question
Hi Bjorn, > currently the following two lines of code with integer variables get compiled completely differently: > > if (d0<tmp) d0=tmp; there must be something else going on because this void bar(int); void foo(int d0, int tmp) { if (d0 < tmp) d0=tmp; bar(d0); } when compiled like this clang -S -O4 -o - sel.c gives this define void @foo(i32 %d0, i32 %tmp) nounwind
2016 Feb 01
2
[Hexagon] Failure to disassemble some new-value instructions
Dear list, I noticed that the Hexagon disassembler has issues with disassembling some firmwares I have. When tracing one of these problems, the handling of some new-value instructions in HexagonDisassembler::getSingleInstruction() turned out to be the cause, specifically this statement: [lines 384-386 in HexagonDisassembler.cpp in HEAD] else if (SubregBit) // Subreg bit should not be