search for: vreg23

...;def> = COPY %C1_X; R600_Reg32:%vreg18 %vreg19:sel_x<def,read-undef> = COPY %vreg14<kill>; R600_Reg128:%vreg19 R600_TReg32:%vreg14 %vreg2<def> = COPY %C1_Y; R600_Reg32:%vreg2 %vreg21:sel_x<def,read-undef> = COPY %vreg18<kill>; R600_Reg128:%vreg21 R600_Reg32:%vreg18 %vreg23<def> = COPY %vreg19<kill>; R600_Reg128:%vreg23,%vreg19 %vreg23:sel_y<def> = COPY %vreg15<kill>; R600_Reg128:%vreg23 R600_TReg32:%vreg15 %vreg24<def> = COPY %vreg21<kill>; R600_Reg128:%vreg24,%vreg21 %vreg24:sel_y<def> = COPY %vreg2; R600_Reg128:%vreg24 R600...

Hi Vincent, On 25/10/2012 18:14, Vincent Lejeune wrote: > When examining the debug output of regalloc, it seems that joining 32bits reg also joins 128 parent reg. > > If I look at the : > %vreg34<def> = COPY %vreg6:sel_y; R600_Reg32:%vreg34 R600_Reg128:%vreg6 > > instructions ; it gets joined to : > 928B%vreg34<def> = COPY %vreg48:sel_y; > > when vreg6 and

...X; R600_Reg32:%vreg18 > %vreg19:sel_x<def,read-undef> = COPY %vreg14<kill>; R600_Reg128:%vreg19 R600_TReg32:%vreg14 > %vreg2<def> = COPY %C1_Y; R600_Reg32:%vreg2 > %vreg21:sel_x<def,read-undef> = COPY %vreg18<kill>; R600_Reg128:%vreg21 R600_Reg32:%vreg18 > %vreg23<def> = COPY %vreg19<kill>; R600_Reg128:%vreg23,%vreg19 > %vreg23:sel_y<def> = COPY %vreg15<kill>; R600_Reg128:%vreg23 R600_TReg32:%vreg15 > %vreg24<def> = COPY %vreg21<kill>; R600_Reg128:%vreg24,%vreg21 > %vreg24:sel_y<def> = COPY %vreg2; R600_Reg1...

...0_Reg128:%vreg19 R600_TReg32:%vreg14 register: %vreg19 +[96r,144r:0) 112B%vreg2<def> = COPY %C1_Y; R600_Reg32:%vreg2 register: %vreg2 +[112r,400r:0) 128B%vreg21:sel_x<def,read-undef> = COPY %vreg18<kill>; R600_Reg128:%vreg21 R600_Reg32:%vreg18 register: %vreg21 +[128r,176r:0) 144B%vreg23<def> = COPY %vreg19<kill>; R600_Reg128:%vreg23,%vreg19 register: %vreg23 +[144r,224r:0) 160B%vreg23:sel_y<def> = COPY %vreg15<kill>; R600_Reg128:%vreg23 R600_TReg32:%vreg15 register: %vreg23 replace range with [144r,160r:1) RESULT: [144r,160r:1)[160r,224r:0)  0 at 160r 1 at...

...> register: %vreg19 +[96r,144r:0) > 112B%vreg2<def> = COPY %C1_Y; R600_Reg32:%vreg2 > register: %vreg2 +[112r,400r:0) > 128B%vreg21:sel_x<def,read-undef> = COPY %vreg18<kill>; > R600_Reg128:%vreg21 R600_Reg32:%vreg18 > register: %vreg21 +[128r,176r:0) > 144B%vreg23<def> = COPY %vreg19<kill>; R600_Reg128:%vreg23,%vreg19 > register: %vreg23 +[144r,224r:0) > 160B%vreg23:sel_y<def> = COPY %vreg15<kill>; R600_Reg128:%vreg23 > R600_TReg32:%vreg15 > register: %vreg23 replace range with [144r,160r:1) RESULT: > [144r,160r:1)[16...

...2:%vreg14 > %vreg2<def> = R600_LOAD_CONST 5; R600_Reg32:%vreg2 > %vreg22<def> = IMPLICIT_DEF; R600_Reg128:%vreg22 > %vreg21<def,tied1> = INSERT_SUBREG %vreg22<tied0>, %vreg18<kill>, sel_x; R600_Reg128:%vreg21,%vreg22 R600_Reg32:%vreg18 > RESERVE_REG 0 > %vreg23<def,tied1> = INSERT_SUBREG %vreg19<tied0>, %vreg15, sel_y; R600_Reg128:%vreg23,%vreg19 R600_TReg32:%vreg15 > %vreg24<def,tied1> = INSERT_SUBREG %vreg21<tied0>, %vreg2, sel_y; R600_Reg128:%vreg24,%vreg21 R600_Reg32:%vreg2 > %vreg25<def> = R600_LOAD_CONST 6; R600_R...

...vreg19,%vreg20 R600_TReg32:%vreg14 %vreg2<def> = R600_LOAD_CONST 5; R600_Reg32:%vreg2 %vreg22<def> = IMPLICIT_DEF; R600_Reg128:%vreg22 %vreg21<def,tied1> = INSERT_SUBREG %vreg22<tied0>, %vreg18<kill>, sel_x; R600_Reg128:%vreg21,%vreg22 R600_Reg32:%vreg18 RESERVE_REG 0 %vreg23<def,tied1> = INSERT_SUBREG %vreg19<tied0>, %vreg15, sel_y; R600_Reg128:%vreg23,%vreg19 R600_TReg32:%vreg15 %vreg24<def,tied1> = INSERT_SUBREG %vreg21<tied0>, %vreg2, sel_y; R600_Reg128:%vreg24,%vreg21 R600_Reg32:%vreg2 %vreg25<def> = R600_LOAD_CONST 6; R600_Reg32:%vreg...

...and register allocation of the above piece of code: ===== Instruction selection ends: Selected selection DAG: BB#3 'foo:vector.body.preheader' SelectionDAG has 11 nodes: t0: ch = EntryToken t1: i64 = MOV_ri TargetConstant:i64<0> t3: ch = CopyToReg t0, Register:i64 %vreg23, t1 t11: v8i64 = VLOAD_D TargetConstant:i64<0> t6: ch = CopyToReg t0, Register:v8i64 %vreg24, t11 t8: ch = TokenFactor t3, t6 t9: ch = JMP BasicBlock:ch<vector.body 0xa61440>, t8 [...] Spilling live registers at end of block. Spilling %vreg31 in %R0 to stack sl...

...real copies that was being generated in your experience? Something that I noticed when experimenting with LLVM on our out-of-tree backend, was that there are copy instructions generated **because of** modulo scheduling. For example before modulo scheduling I have %vreg6<def> = PHI %vreg23, <BB#1>, %vreg17 %vreg25<def> = INSN1 %vreg1, %vreg6; % vreg26<def> = INSN1 %vreg2, %vreg6 <-- same opcode as previous insn % vreg17<def> = INSN2 %vreg6, %vreg5; So for the phi node here, if we do phi elimination and register coalescing, we won't have any c...

Hi - I replied to the original sender only by mistake. Sorry about that. When we started working on the pipeliner, and added it before the scheduler, we also were concerned that the scheduler or other passes would undo the work of the pipeliner. The initial thought was that we would add information (using metadata or some other way like you've suggested) to the basic block to tell the

...e above piece of code: > ===== Instruction selection ends: > Selected selection DAG: BB#3 'foo:vector.body.preheader' > SelectionDAG has 11 nodes: > t0: ch = EntryToken > t1: i64 = MOV_ri TargetConstant:i64<0> > t3: ch = CopyToReg t0, Register:i64 %vreg23, t1 > t11: v8i64 = VLOAD_D TargetConstant:i64<0> > t6: ch = CopyToReg t0, Register:v8i64 %vreg24, t11 > t8: ch = TokenFactor t3, t6 > t9: ch = JMP BasicBlock:ch<vector.body 0xa61440>, t8 > > [...] > > Spilling live registers at end of bl...

...Register:i64 %vreg21, t22 t23: i64 = extract_vector_elt t16, Constant:i64<6> t38: ch = CopyToReg t0, Register:i64 %vreg22, t23 t24: i64 = extract_vector_elt t16, Constant:i64<7> t40: ch = CopyToReg t0, Register:i64 %vreg23, t24 t41: ch = TokenFactor t26, t28, t30, t32, t34, t36, t38, t40 t57: i64 = extract_vector_elt t56, Constant:i64<0> t66: ch = CopyToReg t0, Register:i64 %vreg24, t57 t58: i64 = extract_vector_elt t56, Constant:i64<1>...

Hi, I have some questions about the implementation of Software pipeline in MachinePipeliner.cpp. First, in hexagon backend, between MachinePipeliner and regalloc pass, there're some other passes like phi eliminate, two-address, register coalescing, which may change or insert intructions like 'copy' in MBB, and swp kernel loop may be destroyed by these passes. Why not put