Displaying 2 results from an estimated 2 matches for "subregclass2".
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subregclass
2007 Apr 23
0
[LLVMdev] Register based vector insert/extract
...r1024 = X86_LOADi16 ... ;; r1024 is i16
r1026 = ADDi8 r1024[subreg #0], 42
More specifically, we want to be able to define, for each register class,
a set of subregister classes. In the X86 world, the 64-bit register
classes could have subregclass0 = i8 parts, subregclass1 = i16 parts,
subregclass2 = i32 parts. Each <physreg, subreg#> pair should map to
another physreg (e.g. <RAX,1> -> AX).
The idea of this is that the register allocator allocates registers like
normal, but when it does the rewriting pass, when it replaces vregs with
pregs (e.g. r1024 with CX in this examp...
2007 Apr 23
2
[LLVMdev] Register based vector insert/extract
On Apr 23, 2007, at 1:43 PM, Christopher Lamb wrote:
> On Apr 23, 2007, at 1:17 PM, Christopher Lamb wrote:
>
>> On Apr 23, 2007, at 12:31 PM, Chris Lattner wrote:
>>
>>> On Mon, 23 Apr 2007, Christopher Lamb wrote:
>>>> How can one let the back end know how to insert and extract
>>>> elements of
>>>> a vector through sub-register