search for: dquad

Displaying 3 results from an estimated 3 matches for "dquad".

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2013 Mar 05
2
Function completely locks up my computer if the input is too big
...,2]),] # shift.x<- shift.frame.val[1] * -1 # shift.y<- shift.frame.val[2] * -1 # x<-xy$x + shift.x # y<-xy$y + shift.y # } # name <- c('x', 'y') # xy<-list(x,y) # names(xy)<-name xy } x <- seq(0,5, .5) y <- seq(0,5, .5) z <- seq(0,5, .5) dquad<-expand.grid(x,y,z) name<-c("y","x","z") names(dquad)<-name plot(dquad$x, dquad$y, xlim=c(-25,25), ylim=c(-25,25)) #this works fine rotated<-rotate(dquad$x, dquad$y, 45) points(rotated$x, rotated$y, col='green') # profiling of both time...
2014 Mar 26
19
[LLVMdev] 3.4.1 Release Plans
Hi, We are now about halfway between the 3.4 and 3.5 releases, and I would like to start preparing for a 3.4.1 release. Here is my proposed release schedule: Mar 26 - April 9: Identify and backport additional bug fixes to the 3.4 branch. April 9 - April 18: Testing Phase April 18: 3.4.1 Release How you can help: - If you have any bug fixes you think should be included to 3.4.1, send me an
2013 Aug 08
14
[LLVMdev] [global-isel] Proposal for a global instruction selector
...types via ldrh/strh to GPR. (i16, f16, v1i16, v2i8, ...) All 32-bit types via ldr/str to GPR and vldr/vstr to SPR. All 64-bit types via ldrd/strd to GPRPair and vldr/vstr to DPR. All 128-bit types via vld1/vst1 to DPair. All 192-bit types via vld1/vst1 to DTriple. All 256-bit types via vld1/vst1 to DQuad. This larger set of legal types also makes it easier to handle things like extractelement <8 x i8> which currently produces an illegal type and is thus obfuscated by the type legalizer. An i8 live range could exist in an ARM function as long as the value is only loaded and stored. We could e...