Nouveau - Sep 2019 - [RFC PATCH] clk: Remove BYPASS_PLL_CHECK from PLLs

I have looked at problem with Fermi GPUs where changing to higher clock
led to really bad perfomance (with GpuTest 20x worse perfomance) and later also
crashes of the nouveau. It seemed
to be affected by Shader Clock in Voltage Entries in the video BIOS. Disabling
BYPASS_PLL_CHECK in CLK0_CTRL seems to completely fix the issue. I have
tried to search this BYPASS_PLL_CHECK in Nvidia traces but seemed it
wasn't used nowhere for CLK settings.

Removing this works fine, but I don't know what it's really for.
Actual bit setting this BYPASS_PLL_CHECK is on 0x10:
	lookup -ac0 0x137000 0x10
	PCLOCK.CLK0_CTRL => { BYPASS_PLL_CHECK | UNK12 = 0 }
Also, disabling this bit on other CLKs doesn't seem to break anything.
Tested with GF119 NVS 310.

Signed-off-by: Mark Menzynski <mmenzyns at redhat.com>
---
 drm/nouveau/nvkm/subdev/clk/gf100.c | 8 --------
 drm/nouveau/nvkm/subdev/clk/gk104.c | 8 --------
 2 files changed, 16 deletions(-)

diff --git a/drm/nouveau/nvkm/subdev/clk/gf100.c
b/drm/nouveau/nvkm/subdev/clk/gf100.c
index 7f67f9f5..7ba2a000 100644
--- a/drm/nouveau/nvkm/subdev/clk/gf100.c
+++ b/drm/nouveau/nvkm/subdev/clk/gf100.c
@@ -375,14 +375,6 @@ gf100_clk_prog_2(struct gf100_clk *clk, int idx)
 			nvkm_wr32(device, addr + 0x04, info->coef);
 			nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000001);
 
-			/* Test PLL lock */
-			nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000000);
-			nvkm_msec(device, 2000,
-				if (nvkm_rd32(device, addr + 0x00) & 0x00020000)
-					break;
-			);
-			nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000010);
-
 			/* Enable sync mode */
 			nvkm_mask(device, addr + 0x00, 0x00000004, 0x00000004);
 		}
diff --git a/drm/nouveau/nvkm/subdev/clk/gk104.c
b/drm/nouveau/nvkm/subdev/clk/gk104.c
index 0b37e3da..3a07e032 100644
--- a/drm/nouveau/nvkm/subdev/clk/gk104.c
+++ b/drm/nouveau/nvkm/subdev/clk/gk104.c
@@ -394,14 +394,6 @@ gk104_clk_prog_2(struct gk104_clk *clk, int idx)
 		nvkm_wr32(device, addr + 0x04, info->coef);
 		nvkm_mask(device, addr + 0x00, 0x00000001, 0x00000001);
 
-		/* Test PLL lock */
-		nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000000);
-		nvkm_msec(device, 2000,
-			if (nvkm_rd32(device, addr + 0x00) & 0x00020000)
-				break;
-		);
-		nvkm_mask(device, addr + 0x00, 0x00000010, 0x00000010);
-
 		/* Enable sync mode */
 		nvkm_mask(device, addr + 0x00, 0x00000004, 0x00000004);
 	}
-- 
2.21.0