LaPolla, Justin Anthony via llvm-dev
2021-Sep-30 16:46 UTC
[llvm-dev] [AArch64] Instructions missing MayRaiseFPException flag
There are many instructions in the generated AArch64GenInstrInfo.inc which may raise a floating-point exception, but do not have the MayRaiseFPException flag. For example, consider FADDSrr (FADD single-precision register-to-register): sed '/.* \/\/ Inst #[0-9]\+ = FADDSrr/!d' AArch64GenInstrInfo.inc { 1595, 3, 1, 4, 441, 0, 0x0ULL, nullptr, nullptr, OperandInfo212 }, // Inst #1595 = FADDSrr The ISA reference clearly states This instruction can generate a floating-point exception. https://developer.arm.com/documentation/ddi0596/2021-06/SIMD-FP-Instructions/FADD--scalar---Floating-point-Add--scalar--?lang=en 1. Why doesn't this instruction have the MayRaiseFPException flag? 2. I would like to add the MayRaiseFPException flag to AArch64 instructions which may raise floating-point exceptions. Are there any objections? -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20210930/8bc40f11/attachment.html>