llvm dev - Jan 2021 - [X86] Is it possible to implicitly promote a virtual subregister to a super?

Hi All,

Suppose I have in X86 MIR SSA:

Register WideReg = MRI->createVirtualRegister(&X86::GR32RegClass);
Register NarrowReg = MRI->createVirtualRegister(&X86::GR16RegClass);
// Generate other instructions that def WideReg and NarrowReg
BuildMI(MBB, InsertPt, Loc, TII->get(CMP32rr), WideReg).addReg(NarrowReg);

The above will not pass with --verify-machineinstrs and the CMP32rr will print
to something like:

// other instructions that def %ax and %ebx
cmpl %ax, %ebx

Is it possible to implicitly "promote" (for lack of a better word) the
16-bit GPR into its 32-bit super? The output should look like:

// other instructions that def %ax and %ebx
cmpl %eax, %ebx

Thanks in advance,

Scott Constable
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On Wed, 20 Jan 2021 at 15:53, Constable, Scott D via llvm-dev
<llvm-dev at lists.llvm.org> wrote:
> The above will not pass with --verify-machineinstrs and the CMP32rr will
print to something like:
>
> cmpl %ax, %ebx
>
> Is it possible to implicitly “promote” (for lack of a better word) the
16-bit GPR into its 32-bit super?
Not implicitly, you need another vreg with class GR32 and some
operation to widen the narrow one. And actually you probably need that
to be a real sign/zero extension or something because I don't think
x86 clears the high bits of eax when writing to ax, does it?

If it was 32 -> 64 bit, I think the rules are different and rax would
be zero-extended automatically. In that case you could use a
SUBREG_TO_REG which would eventually go away.

Cheers.

Tim.