llvm dev - Apr 2019 - LLVM back end for the research Connex SIMD processor and GSoC19

Hello.
     I'd like to advertise the LLVM back end I developed in the last 2 years
for the
research Connex wide SIMD processor, which can have up to 4096 lanes. The Connex
SIMD
processor is designed to run efficiently BLAS routins, is an easily
reconfigurable
low-power processor with scratchpad memory, a shift register for inter-lane
communication,
a hardware sum-reduction tree and predictable performance - you can find details
about it
at this address: http://users.dcae.pub.ro/~gstefan/2ndLevel/connex.html . The
processor
has a clean design and its Verilog source code could be made open-source.

     You can find the source code of the latest version of the compiler (LLVM
back end and
extensions for Connex in the LoopVectorize module, etc) and runtime I develop
for the
Connex SIMD processor at this address: 
https://sites.google.com/site/alexsusu/myfilecabinet/OpincaaLLVM_REPO.zip . I
would like
to commit the Connex back end in the very near future in the LLVM repository.
      Also, the Opincaa runtime assembler library contains a great Connex SIMD
processor
simulator, which can be used in case you don't have access to the real
processor.

     Please let me know if you are interested in contributing to this work -
there are
plenty of interesting things to be done, closely related to research to
compilers and
high-level synthesis.

     Some papers that describe the compiler and the processor are available at: 
https://sites.google.com/site/alexsusu/myfilecabinet/OpincaaLLVM_compiler.pdf
and
https://software.intel.com/sites/default/files/managed/d8/cd/catc17-source-to-source-vectorizer-connex-simd-accelerator.pdf
.
     Please don't hesitate to say if you have any questions or feedback.

   Thank you,
     Alex

Hello.
     I would like to come back again to advertise the back end for the Connex
SIMD processor.
     We were kindly accepted by the LLVM foundation as a GSoC 2019 project: 
http://llvm.org/OpenProjects.html#connex_back_end - please let us know if you
want to
contribute to this work, especially as part of the Google Summer of Code 2019.
     The Connex ISA is available at 
https://gitlab.dcae.pub.ro/research/ConnexRelated/opincaa/blob/master/ConnexISA.pdf
.

     Some papers that describe the compiler and the Connex processor are
available at:
       
https://sites.google.com/site/alexsusu/myfilecabinet/OpincaaLLVM_TR_UPB.pdf
        https://dl.acm.org/citation.cfm?id=3306166

     I've just started pushing a patch for the Connex back end at 
https://reviews.llvm.org/D60052 .
     We also have a nice simulator for Connex written in C++ as part of the
Opincaa Connex
assembler at: https://gitlab.dcae.pub.ro/research/ConnexRelated/opincaa/ .

     Please don't hesitate to say if you have any questions or feedback.

   Best regards,
     Alex


On 4/4/2018 12:41 PM, Alex Susu wrote:
>   Hello.
>     I'd like to advertise the LLVM back end I developed in the last 2
years for the
> research Connex wide SIMD processor, which can have up to 4096 lanes. The
Connex SIMD
> processor is designed to run efficiently BLAS routines, is an easily
reconfigurable
> low-power processor with scratchpad memory, a shift register for inter-lane
communication,
> a hardware sum-reduction tree and predictable performance - you can find
details about it
> at this address: http://users.dcae.pub.ro/~gstefan/2ndLevel/connex.html .
The processor
> has a clean design and its Verilog source code could be made open-source.
>
>     You can find the source code of the latest version of the compiler
(LLVM back end and
> extensions for Connex in the LoopVectorize module, etc) and runtime I
develop for the
> Connex SIMD processor at this address:
> https://sites.google.com/site/alexsusu/myfilecabinet/OpincaaLLVM_REPO.zip .
I would like
> to commit the Connex back end in the very near future in the LLVM
repository.
>      Also, the Opincaa runtime assembler library contains a great Connex
SIMD processor
> simulator, which can be used in case you don't have access to the real
processor.
>
>     Please let me know if you are interested in contributing to this work -
there are
> plenty of interesting things to be done, closely related to research to
compilers and
> high-level synthesis.
>
>     Some papers that describe the compiler and the processor are available
at:
>
https://sites.google.com/site/alexsusu/myfilecabinet/OpincaaLLVM_compiler.pdf
and
>
https://software.intel.com/sites/default/files/managed/d8/cd/catc17-source-to-source-vectorizer-connex-simd-accelerator.pdf
> .
>     Please don't hesitate to say if you have any questions or feedback.
>
>   Thank you,
>     Alex

Dear prospective GSoC students, dear LLVMers,

On behalf of the LLVM Foundation I have to provide some clarifications
here to make the situation clear.
>      I would like to come back again to advertise the back end for the
Connex SIMD processor.
>      We were kindly accepted by the LLVM foundation as a GSoC 2019 project:
> http://llvm.org/OpenProjects.html#connex_back_end - please let us know if
you want to
> contribute to this work, especially as part of the Google Summer of Code
2019.
This is not quite true. The LLVM Foundation never accepted this
project. The reason is simple – there is no acceptance procedure and
therefore the above statement is misleading.

I need to remind that the participation in the Google Summer of Code
is twofold: bringing students to LLVM via well-defined summer projects
and doing something useful for the project itself, therefore the
project should be connected to LLVM Compiler Infrastructure
components.

Hope this makes everything clear.
-- 
With best regards, Anton Korobeynikov
Department of Statistical Modelling, Saint Petersburg State University