llvm dev - Mar 2019 - How to build an ARM Thumb2 ADD with shift immediate Machine Instruction

Hello,

I’m trying to build an "ADD with shift immediate" machine instruction
(ADD(register) Encoding T3; item A7.7.4 of the ARMv7-M manual) in an ARM machine
function pass. Here is my code

    BuildMI(...., TII->get(ARM::t2ADDrs),
r1).addReg(r1).addReg(r1).addReg(r2).addImm(imm);

This code can compile, but  I got a failed assertion
     Assertion `idx < size()' failed.
thrown by llvm/include/llvm/ADT/SmallVector.h. when I compile test program with
the pass.

I tried to tweak the registers and immediates added to the BuildMI() but
haven't succeeded.

Can anyone give me some direction on how to tackle this problem?

Also, can anyone explain to me what
    pred:14
and
   pred:%noreg
mean in ARM machine instructions? I see them everywhere.

Thanks,
-Jie

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https://github.com/llvm/llvm-project/blob/7a8e505/llvm/lib/Target/ARM/ARMISelLowering.cpp#L8481
has the correct invocation.  You should have been able to find this using
“grep”.  More generally, if you’re curious how an instruction is represented,
you can instruct the compiler to print the IR/MIR for a file at various stages
using “-print-after-all” (“-mllvm -print-after-all” from clang).

ARM supports conditional execution; the predicate operands are used to represent
that.  This is represented with two operands; the predicate code (“al”, “eq”,
“ne”, etc.), and the register that controls predication (%noreg if it’s not
predicated, $cpsr if it is).

-Eli

From: llvm-dev <llvm-dev-bounces at lists.llvm.org> On Behalf Of Jie Zhou
via llvm-dev
Sent: Wednesday, March 20, 2019 5:53 PM
To: via llvm-dev <llvm-dev at lists.llvm.org>
Subject: [EXT] [llvm-dev] How to build an ARM Thumb2 ADD with shift immediate
Machine Instruction

Hello,

I’m trying to build an "ADD with shift immediate" machine instruction
(ADD(register) Encoding T3; item A7.7.4 of the ARMv7-M manual) in an ARM machine
function pass. Here is my code

    BuildMI(...., TII->get(ARM::t2ADDrs),
r1).addReg(r1).addReg(r1).addReg(r2).addImm(imm);

This code can compile, but  I got a failed assertion
     Assertion `idx < size()' failed.
thrown by llvm/include/llvm/ADT/SmallVector.h. when I compile test program with
the pass.

I tried to tweak the registers and immediates added to the BuildMI() but
haven't succeeded.

Can anyone give me some direction on how to tackle this problem?

Also, can anyone explain to me what
    pred:14
and
   pred:%noreg
mean in ARM machine instructions? I see them everywhere.

Thanks,
-Jie

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