Alex Susu via llvm-dev
2019-Mar-06 00:01 UTC
[llvm-dev] Compile for ARM SVE with the latest LLVM
Hello. I would like to build some examples for ARM SVE. I see the support for SVE is available in the AArch64 back end of the latest LLVM. So I thought of using the latest LLVM distribution (revision 352287 from Jan 2019) and not rely on the ARM HPC compiler from https://developer.arm.com/products/software-development-tools/hpc/arm-cpp-compiler. Following https://static.docs.arm.com/100891/0608/scalable_vector_extension_guide_100891_0608_00_en.pdf, at page 2-17, I give this command: clang -O3 --target=aarch64-arm-none-eabi -march=armv8-a+sve -S test.c -mllvm -debug # -emit-llvm However, the resulting .s (or .ll file) does not contain code for ARM SVE, but vector code ARM NEON. Is there something I'm missing? Or do I really have to use ARM's HPC compiler? Thank you very much, Alex
Renato Golin via llvm-dev
2019-Mar-06 13:21 UTC
[llvm-dev] Compile for ARM SVE with the latest LLVM
On Wed, 6 Mar 2019 at 00:01, Alex Susu via llvm-dev <llvm-dev at lists.llvm.org> wrote:> I would like to build some examples for ARM SVE. > I see the support for SVE is available in the AArch64 back end of the latest LLVM. > So I thought of using the latest LLVM distribution (revision 352287 from Jan 2019) > and not rely on the ARM HPC compiler from > https://developer.arm.com/products/software-development-tools/hpc/arm-cpp-compiler.Hi Alex, There is SVE support in the back-end, so we can consume and generate SVE code, though I'm not sure what completion level it is, but user interaction with SVE is restricted to generating (asm) code snippets by hand and passing it directly to the back-end. There is no IR support for scalable vectors yet, though this is being discussed with the RISC-V folks, to make sure we get something that works for everyone. There is no IR lowering into MIR, which will only be possible once we know how the IR will look like. There is no vectorisation support for scalable vectors (SVE or otherwise), so simple loops will never be turned into SVE, even after we have all the above. This, again, needs all the above problems to have been tackled to be constructively worked on. Alternatives to vectorisation would be either inline ASM (which maybe can already be plugged into, but YMMV) or intrinsics (as covered by the SVE ACLE) which are also not yet supported (same reason, no IR support). In summary, finaliing IR support for SVE would open the other avenues of work, and that's why we're still stuck.> Is there something I'm missing? Or do I really have to use ARM's HPC compiler?You can also use GCC 8+, which has support for SVE vectorisation and does a good job at it. You probably already know but, current upstream QEMU has SVE support (user and system emulation), but it might not have reached your distro yet. cheers, --renato
Graham Hunter via llvm-dev
2019-Mar-06 14:49 UTC
[llvm-dev] Compile for ARM SVE with the latest LLVM
Hi,> There is SVE support in the back-end, so we can consume and generate > SVE code, though I'm not sure what completion level it is, but user > interaction with SVE is restricted to generating (asm) code snippets > by hand and passing it directly to the back-end.There should be full support for .s files. Inline asm won't work as well, since I don't think we've added the constraints for register types.>> Is there something I'm missing? Or do I really have to use ARM's HPC compiler? > > You can also use GCC 8+, which has support for SVE vectorisation and > does a good job at it. You probably already know but, current upstream > QEMU has SVE support (user and system emulation), but it might not > have reached your distro yet.In addition to GCC, Arm has released a subset of the HPC compiler on github: https://github.com/ARM-software/Clang-SVE https://github.com/ARM-software/LLVM-SVE This will support autovectorization, but not the C intrinsics defined in the SVE ACLE. It's based on LLVM 5, so doesn't contain all the features of trunk. -Graham IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
David Greene via llvm-dev
2019-Mar-07 19:18 UTC
[llvm-dev] Compile for ARM SVE with the latest LLVM
Renato Golin via llvm-dev <llvm-dev at lists.llvm.org> writes:> There is no IR support for scalable vectors yet, though this is being > discussed with the RISC-V folks, to make sure we get something that > works for everyone.What is the status of this? It seems to have gone quiet for some time now. What needs to happen to push it forward? -David