hameeza ahmed via llvm-dev
2017-Jul-19 21:47 UTC
[llvm-dev] error:Ran out of lanemask bits to represent subregisterr
I have made changes in 3 files:
LaneBitmask.h, codegenregisters.cpp and miparser.cpp. files are attached
here.
Now i am getting following errors. which means registerinfo.inc file is not
generated successfully.
/PIM/lib/Target/X86/MCTargetDesc/X86BaseInfo.h:733:24: error:
no member named 'XMM8' in namespace 'llvm::X86'
if ((RegNo >= X86::XMM8 && RegNo <= X86::XMM31) ||
fatal error: too many errors emitted, stopping now [-ferror-limit=]
20 errors generated.
When i comment out the line to construct 65536 bit register in
registerinfo.td. it run fine.
What to do?
On Thu, Jul 20, 2017 at 2:36 AM, Krzysztof Parzyszek <
kparzysz at codeaurora.org> wrote:
> Those couldn't be done generically, that's why the asserts were
added.
>
> -Krzysztof
>
> On 7/19/2017 4:30 PM, Craig Topper wrote:
>
>> What about the static asserts protecting a Log call and another in the
>> parser?
>>
>> On Wed, Jul 19, 2017 at 2:26 PM Krzysztof Parzyszek <
>> kparzysz at codeaurora.org <mailto:kparzysz at
codeaurora.org>> wrote:
>>
>> On 7/19/2017 4:18 PM, Craig Topper wrote:
>> > LaneMask isn't as self contained as it should be. 64 bits
is enough
>> > here. The problem is accidental leaking of the current size.
>> >
>> > For example there was a hard coded compare with 32 in
tablegen
>> until I
>> > fixed it recently.
>>
>> This is most likely the only example. I actually tested it with
>> uint64_t (but without exceeding 32 lanes).
>>
>> -Krzysztof
>>
>> --
>> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
>> hosted by The Linux Foundation
>>
>> --
>> ~Craig
>>
>
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted
> by The Linux Foundation
>
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Craig Topper via llvm-dev
2017-Jul-19 22:02 UTC
[llvm-dev] error:Ran out of lanemask bits to represent subregisterr
Can you send the generated registerinfo.inc file as well. ~Craig On Wed, Jul 19, 2017 at 2:47 PM, hameeza ahmed <hahmed2305 at gmail.com> wrote:> I have made changes in 3 files: > LaneBitmask.h, codegenregisters.cpp and miparser.cpp. files are attached > here. > > Now i am getting following errors. which means registerinfo.inc file is > not generated successfully. > > /PIM/lib/Target/X86/MCTargetDesc/X86BaseInfo.h:733:24: error: > no member named 'XMM8' in namespace 'llvm::X86' > if ((RegNo >= X86::XMM8 && RegNo <= X86::XMM31) || > > > fatal error: too many errors emitted, stopping now [-ferror-limit=] > 20 errors generated. > > When i comment out the line to construct 65536 bit register in > registerinfo.td. it run fine. > > What to do? > > On Thu, Jul 20, 2017 at 2:36 AM, Krzysztof Parzyszek < > kparzysz at codeaurora.org> wrote: > >> Those couldn't be done generically, that's why the asserts were added. >> >> -Krzysztof >> >> On 7/19/2017 4:30 PM, Craig Topper wrote: >> >>> What about the static asserts protecting a Log call and another in the >>> parser? >>> >>> On Wed, Jul 19, 2017 at 2:26 PM Krzysztof Parzyszek < >>> kparzysz at codeaurora.org <mailto:kparzysz at codeaurora.org>> wrote: >>> >>> On 7/19/2017 4:18 PM, Craig Topper wrote: >>> > LaneMask isn't as self contained as it should be. 64 bits is >>> enough >>> > here. The problem is accidental leaking of the current size. >>> > >>> > For example there was a hard coded compare with 32 in tablegen >>> until I >>> > fixed it recently. >>> >>> This is most likely the only example. I actually tested it with >>> uint64_t (but without exceeding 32 lanes). >>> >>> -Krzysztof >>> >>> -- >>> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, >>> hosted by The Linux Foundation >>> >>> -- >>> ~Craig >>> >> >> -- >> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted >> by The Linux Foundation >> > >-------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20170719/637835c7/attachment.html>
hameeza ahmed via llvm-dev
2017-Jul-19 22:04 UTC
[llvm-dev] error:Ran out of lanemask bits to represent subregisterr
the file is not generated thats why getting such errors On Jul 19, 2017 10:02 PM, "Craig Topper" <craig.topper at gmail.com> wrote:> Can you send the generated registerinfo.inc file as well. > > ~Craig > > On Wed, Jul 19, 2017 at 2:47 PM, hameeza ahmed <hahmed2305 at gmail.com> > wrote: > >> I have made changes in 3 files: >> LaneBitmask.h, codegenregisters.cpp and miparser.cpp. files are attached >> here. >> >> Now i am getting following errors. which means registerinfo.inc file is >> not generated successfully. >> >> /PIM/lib/Target/X86/MCTargetDesc/X86BaseInfo.h:733:24: error: >> no member named 'XMM8' in namespace 'llvm::X86' >> if ((RegNo >= X86::XMM8 && RegNo <= X86::XMM31) || >> >> >> fatal error: too many errors emitted, stopping now [-ferror-limit=] >> 20 errors generated. >> >> When i comment out the line to construct 65536 bit register in >> registerinfo.td. it run fine. >> >> What to do? >> >> On Thu, Jul 20, 2017 at 2:36 AM, Krzysztof Parzyszek < >> kparzysz at codeaurora.org> wrote: >> >>> Those couldn't be done generically, that's why the asserts were added. >>> >>> -Krzysztof >>> >>> On 7/19/2017 4:30 PM, Craig Topper wrote: >>> >>>> What about the static asserts protecting a Log call and another in the >>>> parser? >>>> >>>> On Wed, Jul 19, 2017 at 2:26 PM Krzysztof Parzyszek < >>>> kparzysz at codeaurora.org <mailto:kparzysz at codeaurora.org>> wrote: >>>> >>>> On 7/19/2017 4:18 PM, Craig Topper wrote: >>>> > LaneMask isn't as self contained as it should be. 64 bits is >>>> enough >>>> > here. The problem is accidental leaking of the current size. >>>> > >>>> > For example there was a hard coded compare with 32 in tablegen >>>> until I >>>> > fixed it recently. >>>> >>>> This is most likely the only example. I actually tested it with >>>> uint64_t (but without exceeding 32 lanes). >>>> >>>> -Krzysztof >>>> >>>> -- >>>> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, >>>> hosted by The Linux Foundation >>>> >>>> -- >>>> ~Craig >>>> >>> >>> -- >>> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, >>> hosted by The Linux Foundation >>> >> >> >-------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20170720/c2746608/attachment.html>
Krzysztof Parzyszek via llvm-dev
2017-Jul-19 22:04 UTC
[llvm-dev] error:Ran out of lanemask bits to represent subregisterr
Could you share your .td file? Also, could you generate the .inc file by hand and show the output? You could use something like this to generate it: llvm-tblgen -gen-register-info -I.../lib/Target/<your-target> -I.../lib/Target -I.../include/llvm/Target <your-target>.td -o - What is the relationship of your target with X86? Are you trying to add something to it, or are you working on a separate target? -Krzysztof On 7/19/2017 4:47 PM, hameeza ahmed wrote:> I have made changes in 3 files: > LaneBitmask.h, codegenregisters.cpp and miparser.cpp. files are attached > here. > > Now i am getting following errors. which means registerinfo.inc file is > not generated successfully. > > /PIM/lib/Target/X86/MCTargetDesc/X86BaseInfo.h:733:24: error: > no member named 'XMM8' in namespace 'llvm::X86' > if ((RegNo >= X86::XMM8 && RegNo <= X86::XMM31) || > > > fatal error: too many errors emitted, stopping now [-ferror-limit=] > 20 errors generated. > > When i comment out the line to construct 65536 bit register in > registerinfo.td <http://registerinfo.td>. it run fine. > > What to do? > > On Thu, Jul 20, 2017 at 2:36 AM, Krzysztof Parzyszek > <kparzysz at codeaurora.org <mailto:kparzysz at codeaurora.org>> wrote: > > Those couldn't be done generically, that's why the asserts were added. > > -Krzysztof > > On 7/19/2017 4:30 PM, Craig Topper wrote: > > What about the static asserts protecting a Log call and another > in the parser? > > On Wed, Jul 19, 2017 at 2:26 PM Krzysztof Parzyszek > <kparzysz at codeaurora.org <mailto:kparzysz at codeaurora.org> > <mailto:kparzysz at codeaurora.org > <mailto:kparzysz at codeaurora.org>>> wrote: > > On 7/19/2017 4:18 PM, Craig Topper wrote: > > LaneMask isn't as self contained as it should be. 64 > bits is enough > > here. The problem is accidental leaking of the current size. > > > > For example there was a hard coded compare with 32 in > tablegen > until I > > fixed it recently. > > This is most likely the only example. I actually tested it > with > uint64_t (but without exceeding 32 lanes). > > -Krzysztof > > -- > Qualcomm Innovation Center, Inc. is a member of Code Aurora > Forum, > hosted by The Linux Foundation > > -- > ~Craig > > > -- > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, > hosted by The Linux Foundation > >-- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Craig Topper via llvm-dev
2017-Jul-19 22:07 UTC
[llvm-dev] error:Ran out of lanemask bits to represent subregisterr
Also every line in CodeGenRegisters.cpp that does something like this Idx.LaneMask = LaneBitmask(1 << Bit); Needs to use 1ULL instead of just 1. Alternatively use my patch from r308042. ~Craig On Wed, Jul 19, 2017 at 3:04 PM, Krzysztof Parzyszek < kparzysz at codeaurora.org> wrote:> Could you share your .td file? > > Also, could you generate the .inc file by hand and show the output? > > You could use something like this to generate it: > llvm-tblgen -gen-register-info -I.../lib/Target/<your-target> > -I.../lib/Target -I.../include/llvm/Target <your-target>.td -o - > > What is the relationship of your target with X86? Are you trying to add > something to it, or are you working on a separate target? > > -Krzysztof > > On 7/19/2017 4:47 PM, hameeza ahmed wrote: > >> I have made changes in 3 files: >> LaneBitmask.h, codegenregisters.cpp and miparser.cpp. files are attached >> here. >> >> Now i am getting following errors. which means registerinfo.inc file is >> not generated successfully. >> >> /PIM/lib/Target/X86/MCTargetDesc/X86BaseInfo.h:733:24: error: >> no member named 'XMM8' in namespace 'llvm::X86' >> if ((RegNo >= X86::XMM8 && RegNo <= X86::XMM31) || >> >> >> fatal error: too many errors emitted, stopping now [-ferror-limit=] >> 20 errors generated. >> >> When i comment out the line to construct 65536 bit register in >> registerinfo.td <http://registerinfo.td>. it run fine. >> >> What to do? >> >> On Thu, Jul 20, 2017 at 2:36 AM, Krzysztof Parzyszek < >> kparzysz at codeaurora.org <mailto:kparzysz at codeaurora.org>> wrote: >> >> Those couldn't be done generically, that's why the asserts were added. >> >> -Krzysztof >> >> On 7/19/2017 4:30 PM, Craig Topper wrote: >> >> What about the static asserts protecting a Log call and another >> in the parser? >> >> On Wed, Jul 19, 2017 at 2:26 PM Krzysztof Parzyszek >> <kparzysz at codeaurora.org <mailto:kparzysz at codeaurora.org> >> <mailto:kparzysz at codeaurora.org >> <mailto:kparzysz at codeaurora.org>>> wrote: >> >> On 7/19/2017 4:18 PM, Craig Topper wrote: >> > LaneMask isn't as self contained as it should be. 64 >> bits is enough >> > here. The problem is accidental leaking of the current >> size. >> > >> > For example there was a hard coded compare with 32 in >> tablegen >> until I >> > fixed it recently. >> >> This is most likely the only example. I actually tested it >> with >> uint64_t (but without exceeding 32 lanes). >> >> -Krzysztof >> >> -- >> Qualcomm Innovation Center, Inc. is a member of Code Aurora >> Forum, >> hosted by The Linux Foundation >> >> -- ~Craig >> >> >> -- Qualcomm Innovation Center, Inc. is a member of Code Aurora >> Forum, >> hosted by The Linux Foundation >> >> >> > -- > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted > by The Linux Foundation >-------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20170719/8a66b419/attachment.html>
hameeza ahmed via llvm-dev
2017-Jul-19 22:08 UTC
[llvm-dev] error:Ran out of lanemask bits to represent subregisterr
My code is attached here. I m trying to add in x86 for my target in this initial phase. Maybe later i will use separate target. On Jul 19, 2017 10:04 PM, "Krzysztof Parzyszek" <kparzysz at codeaurora.org> wrote:> Could you share your .td file? > > Also, could you generate the .inc file by hand and show the output? > > You could use something like this to generate it: > llvm-tblgen -gen-register-info -I.../lib/Target/<your-target> > -I.../lib/Target -I.../include/llvm/Target <your-target>.td -o - > > What is the relationship of your target with X86? Are you trying to add > something to it, or are you working on a separate target? > > -Krzysztof > > On 7/19/2017 4:47 PM, hameeza ahmed wrote: > >> I have made changes in 3 files: >> LaneBitmask.h, codegenregisters.cpp and miparser.cpp. files are attached >> here. >> >> Now i am getting following errors. which means registerinfo.inc file is >> not generated successfully. >> >> /PIM/lib/Target/X86/MCTargetDesc/X86BaseInfo.h:733:24: error: >> no member named 'XMM8' in namespace 'llvm::X86' >> if ((RegNo >= X86::XMM8 && RegNo <= X86::XMM31) || >> >> >> fatal error: too many errors emitted, stopping now [-ferror-limit=] >> 20 errors generated. >> >> When i comment out the line to construct 65536 bit register in >> registerinfo.td <http://registerinfo.td>. it run fine. >> >> What to do? >> >> On Thu, Jul 20, 2017 at 2:36 AM, Krzysztof Parzyszek < >> kparzysz at codeaurora.org <mailto:kparzysz at codeaurora.org>> wrote: >> >> Those couldn't be done generically, that's why the asserts were added. >> >> -Krzysztof >> >> On 7/19/2017 4:30 PM, Craig Topper wrote: >> >> What about the static asserts protecting a Log call and another >> in the parser? >> >> On Wed, Jul 19, 2017 at 2:26 PM Krzysztof Parzyszek >> <kparzysz at codeaurora.org <mailto:kparzysz at codeaurora.org> >> <mailto:kparzysz at codeaurora.org >> <mailto:kparzysz at codeaurora.org>>> wrote: >> >> On 7/19/2017 4:18 PM, Craig Topper wrote: >> > LaneMask isn't as self contained as it should be. 64 >> bits is enough >> > here. The problem is accidental leaking of the current >> size. >> > >> > For example there was a hard coded compare with 32 in >> tablegen >> until I >> > fixed it recently. >> >> This is most likely the only example. I actually tested it >> with >> uint64_t (but without exceeding 32 lanes). >> >> -Krzysztof >> >> -- >> Qualcomm Innovation Center, Inc. is a member of Code Aurora >> Forum, >> hosted by The Linux Foundation >> >> -- ~Craig >> >> >> -- Qualcomm Innovation Center, Inc. is a member of Code Aurora >> Forum, >> hosted by The Linux Foundation >> >> >> > -- > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted > by The Linux Foundation >-------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20170720/76a54c02/attachment.html> -------------- next part -------------- let Namespace = "R" in { def sub_32bit : SubRegIndex<32>; def sub_64bit : SubRegIndex<64>; def sub_128bit : SubRegIndex<128>; def sub_256bit : SubRegIndex<256>; def sub_512bit : SubRegIndex<512>; def sub_1024bit : SubRegIndex<1024>; def sub_2048bit : SubRegIndex<2048>; def sub_2048bit_hi : SubRegIndex<2048, 2048>; def sub_4096bit : SubRegIndex<4096>; def sub_4096bit_hi : SubRegIndex<4096, 4096>; def sub_8192bit : SubRegIndex<8192>; def sub_8192bit_hi : SubRegIndex<8192, 8192>; def sub_16384bit : SubRegIndex<16384>; def sub_16384bit_hi : SubRegIndex<16384, 16384>; def sub_32768bit : SubRegIndex<32768>; def sub_32768bit_hi : SubRegIndex<32768, 32768>; } foreach J = 0-31 in { foreach I = 0-511 in { def R_#J#_REG32b_#I : R_CLASS<"R_" #J# "R32b_"#I, I>, DwarfRegNum<[I]>; } let SubRegIndices = [sub_32bit] in { foreach I = 0-255 in def R_#J#_REG64b_#I : R_CLASS<"R_"#J#"_R64b_"#I, I, [!cast<R_CLASS>("R_"#J#"_REG32b_"#I)]>; } let SubRegIndices = [sub_64bit] in { foreach I = 0-127 in def R_#J#_REG128b_#I : R_CLASS<"R_"#J#"_R128b_"#I, I, [!cast<R_CLASS>("R_"#J#"_REG64b_"#I)]>; } let SubRegIndices = [sub_128bit] in { foreach I = 0-63 in def R_#J#_REG256b_#I : R_CLASS<"R_"#J#"_R256b_"#I, I, [!cast<R_CLASS>("R_"#J#"_REG128b_"#I)]>; } let SubRegIndices = [sub_256bit] in { foreach I = 0-31 in def R_#J#_REG512b_#I : R_CLASS<"R_"#J#"_R512b_"#I, I, [!cast<R_CLASS>("R_"#J#"_REG256b_"#I)]>; } let SubRegIndices = [sub_512bit], CoveredBySubRegs = 1 in { foreach I = 0-15 in def R_#J#_REG1024b_#I : R_CLASS<"R_"#J#"_R1024b_"#I, I, [!cast<R_CLASS>("R_"#J#"_REG512b_"#I)]>; } let SubRegIndices = [sub_1024bit] in { foreach I = 0-7 in def R_#J#_REG2048b_#I : R_CLASS<"R_"#J#"_R2048b_"#I, I, [!cast<R_CLASS>("R_"#J#"_REG1024b_"#I)]>; } } //end of J loop let SubRegIndices = [sub_2048bit, sub_2048bit_hi], CoveredBySubRegs = 1 in { foreach I = 0-7 in { def R_0_1_REG4Kb_#I : R_CLASS<"R_0_1_R4Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_0_REG2048b_"#I), !cast<R_CLASS>("R_1_REG2048b_"#I)]>; def R_2_3_REG4Kb_#I : R_CLASS<"R_2_3_R4Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_2_REG2048b_"#I), !cast<R_CLASS>("R_3_REG2048b_"#I)]>; def R_4_5_REG4Kb_#I : R_CLASS<"R_4_5_R4Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_4_REG2048b_"#I), !cast<R_CLASS>("R_5_REG2048b_"#I)]>; def R_6_7_REG4Kb_#I : R_CLASS<"R_6_7_R4Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_6_REG2048b_"#I), !cast<R_CLASS>("R_7_REG2048b_"#I)]>; def R_8_9_REG4Kb_#I : R_CLASS<"R_8_9_R4Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_8_REG2048b_"#I), !cast<R_CLASS>("R_9_REG2048b_"#I)]>; def R_10_11_REG4Kb_#I : R_CLASS<"R_10_11_R4Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_10_REG2048b_"#I), !cast<R_CLASS>("R_11_REG2048b_"#I)]>; def R_12_13_REG4Kb_#I : R_CLASS<"R_12_13_R4Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_12_REG2048b_"#I), !cast<R_CLASS>("R_13_REG2048b_"#I)]>; def R_14_15_REG4Kb_#I : R_CLASS<"R_14_15_R4Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_14_REG2048b_"#I), !cast<R_CLASS>("R_15_REG2048b_"#I)]>; def R_16_17_REG4Kb_#I : R_CLASS<"R_16_17_R4Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_16_REG2048b_"#I), !cast<R_CLASS>("R_17_REG2048b_"#I)]>; def R_18_19_REG4Kb_#I : R_CLASS<"R_18_19_R4Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_18_REG2048b_"#I), !cast<R_CLASS>("R_19_REG2048b_"#I)]>; def R_20_21_REG4Kb_#I : R_CLASS<"R_20_21_R4Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_20_REG2048b_"#I), !cast<R_CLASS>("R_21_REG2048b_"#I)]>; def R_22_23_REG4Kb_#I : R_CLASS<"R_22_23_R4Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_22_REG2048b_"#I), !cast<R_CLASS>("R_23_REG2048b_"#I)]>; def R_24_25_REG4Kb_#I : R_CLASS<"R_24_25_R4Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_24_REG2048b_"#I), !cast<R_CLASS>("R_25_REG2048b_"#I)]>; def R_26_27_REG4Kb_#I : R_CLASS<"R_26_27_R4Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_26_REG2048b_"#I), !cast<R_CLASS>("R_27_REG2048b_"#I)]>; def R_28_29_REG4Kb_#I : R_CLASS<"R_28_29_R4Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_28_REG2048b_"#I), !cast<R_CLASS>("R_29_REG2048b_"#I)]>; def R_30_31_REG4Kb_#I : R_CLASS<"R_30_31_R4Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_30_REG2048b_"#I), !cast<R_CLASS>("R_31_REG2048b_"#I)]>; } } let SubRegIndices = [sub_4096bit, sub_4096bit_hi], CoveredBySubRegs = 1 in { foreach I = 0-7 in { def R_0_1_2_3_REG8Kb_#I : R_CLASS<"R_0_1_2_3_R8Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_0_1_REG4Kb_"#I), !cast<R_CLASS>("R_2_3_REG4Kb_"#I)]>; def R_4_5_6_7_REG8Kb_#I : R_CLASS<"R_4_5_6_7_R8Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_4_5_REG4Kb_"#I), !cast<R_CLASS>("R_6_7_REG4Kb_"#I)]>; def R_8_9_10_11_REG8Kb_#I : R_CLASS<"R_8_9_10_11_R8Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_8_9_REG4Kb_"#I), !cast<R_CLASS>("R_10_11_REG4Kb_"#I)]>; def R_12_13_14_15_REG8Kb_#I : R_CLASS<"R_12_13_14_15_R8Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_12_13_REG4Kb_"#I), !cast<R_CLASS>("R_14_15_REG4Kb_"#I)]>; def R_16_17_18_19_REG8Kb_#I : R_CLASS<"R_16_17_18_19_R8Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_16_17_REG4Kb_"#I), !cast<R_CLASS>("R_18_19_REG4Kb_"#I)]>; def R_20_21_22_23_REG8Kb_#I : R_CLASS<"R_20_21_22_23_R8Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_20_21_REG4Kb_"#I), !cast<R_CLASS>("R_22_23_REG4Kb_"#I)]>; def R_24_25_26_27_REG8Kb_#I : R_CLASS<"R_24_25_26_27_R8Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_24_25_REG4Kb_"#I), !cast<R_CLASS>("R_26_27_REG4Kb_"#I)]>; def R_28_29_30_31_REG8Kb_#I : R_CLASS<"R_28_29_30_31_R8Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_28_29_REG4Kb_"#I), !cast<R_CLASS>("R_30_31_REG4Kb_"#I)]>; } } let SubRegIndices = [sub_8192bit, sub_8192bit_hi], CoveredBySubRegs = 1 in { foreach I = 0-7 in { def R_0_1_2_3_4_5_6_7_REG16Kb_#I : R_CLASS<"R_0_1_2_3_4_5_6_7_R16Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_0_1_2_3_REG8Kb_"#I), !cast<R_CLASS>("R_4_5_6_7_REG8Kb_"#I)]>; def R_8_9_10_11_12_13_14_15_REG16Kb_#I : R_CLASS<"R_8_9_10_11_12_13_14_15_R16Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_8_9_10_11_REG8Kb_"#I), !cast<R_CLASS>("R_12_13_14_15_REG8Kb_"#I)]>; def R_16_17_18_19_20_21_22_23_REG16Kb_#I : R_CLASS<"R_16_17_18_19_20_21_22_23_R16Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_16_17_18_19_REG8Kb_"#I), !cast<R_CLASS>("R_20_21_22_23_REG8Kb_"#I)]>; def R_24_25_26_27_28_29_30_31_REG16Kb_#I : R_CLASS<"R_24_25_26_27_28_29_30_31_R16Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_24_25_26_27_REG8Kb_"#I), !cast<R_CLASS>("R_28_29_30_31_REG8Kb_"#I)]>; } } let SubRegIndices = [sub_16384bit, sub_16384bit_hi], CoveredBySubRegs = 1 in { foreach I = 0-7 in { def R_0_1_2_3_4_5_6_7_8_9_10_11_12_13_14_15_REG32Kb_#I : R_CLASS<"R_0_1_2_3_4_5_6_7_8_9_10_11_12_13_14_15_R32Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_0_1_2_3_4_5_6_7_REG16Kb_"#I), !cast<R_CLASS>("R_8_9_10_11_12_13_14_15_REG16Kb_"#I)]>; def R_16_17_18_19_20_21_22_23_24_25_26_27_28_29_30_31_REG32Kb_#I : R_CLASS<"R_16_17_18_19_20_21_22_23_24_25_26_27_28_29_30_31_R32Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_16_17_18_19_20_21_22_23_REG16Kb_"#I), !cast<R_CLASS>("R_24_25_26_27_28_29_30_31_REG16Kb_"#I)]>; } } let SubRegIndices = [sub_32768bit, sub_32768bit_hi], CoveredBySubRegs = 1 in { foreach I = 0-7 in def R_0_1_2_3_4_5_6_7_8_9_10_11_12_13_14_15_16_17_18_19_20_21_22_23_24_25_26_27_28_29_30_31_REG64Kb_#I : R_CLASS<"R_0_1_2_3_4_5_6_7_8_9_10_11_12_13_14_15_16_17_18_19_20_21_22_23_24_25_26_27_28_29_30_31_R64Kb_"#I, !shl(I,2), [!cast<R_CLASS>("R_0_1_2_3_4_5_6_7_8_9_10_11_12_13_14_15_REG32Kb_"#I), !cast<R_CLASS>("R_16_17_18_19_20_21_22_23_24_25_26_27_28_29_30_31_REG32Kb_"#I)]>; }