Johnson, Nicholas Paul via llvm-dev
2017-Jun-07 14:12 UTC
[llvm-dev] Clarification: machine operand subreg, <def, read-undef>, and IMPLICIT_DEF
Hey, Suppose I have this MachineInstr: %vreg190:sub_32_1<def,read-undef> = IMPLICIT_DEF; PairRegs:%vreg190 (on my backend, the 'PairRegs' register class hold 2-vectors of i32 values) I want to make sure I understand the combination of subreg and read-undef correctly. According to the comment in MachineOperand.h, quote: /// ... On a sub-register def operand, it refers to the part of the /// register that isn't written. ... So, am I correct to say that the above instruction is equivalent to the following? %vreg190<def> = IMPLICIT_DEF; PairRegs:%vreg190 Or if there is a subtle distinction, please help me understand it. Thank you, Nick Johnson D. E. Shaw Research
Geoff Berry via llvm-dev
2017-Jun-07 14:39 UTC
[llvm-dev] Clarification: machine operand subreg, <def, read-undef>, and IMPLICIT_DEF
I believe the short answer is yes, they are pretty much equivalent, but only because the value being written is IMPLICIT_DEF. The first instruction results in: %vreg190:sub_32_1 -> i32 undef (from IMPLICIT_DEF) %vreg190:sub_32_0? -> i32 undef (from read-undef) The second instruction results in: %vreg190 -> i32 2-vector undef (from IMPLICIT_DEF) Assuming the i32 2-vector can hold any two i32 values, they are equivalent, other than the fact that they will likely generate instructions that write different widths. On 6/7/2017 10:12 AM, Johnson, Nicholas Paul via llvm-dev wrote:> Hey, > > Suppose I have this MachineInstr: > %vreg190:sub_32_1<def,read-undef> = IMPLICIT_DEF; PairRegs:%vreg190 > > (on my backend, the 'PairRegs' register class hold 2-vectors of i32 values) > > I want to make sure I understand the combination of subreg and read-undef correctly. According to the comment in MachineOperand.h, quote: > /// ... On a sub-register def operand, it refers to the part of the > /// register that isn't written. ... > > So, am I correct to say that the above instruction is equivalent to the following? > %vreg190<def> = IMPLICIT_DEF; PairRegs:%vreg190 > > Or if there is a subtle distinction, please help me understand it. > > Thank you, > Nick Johnson > D. E. Shaw Research > > > _______________________________________________ > LLVM Developers mailing list > llvm-dev at lists.llvm.org > http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev-- Geoff Berry Employee of Qualcomm Datacenter Technologies, Inc. Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.