Matt Arsenault via llvm-dev
2016-Oct-13 08:19 UTC
[llvm-dev] Target MachineFunctionInfo and MIR passes
Hi, How are MIR passes supposed to deal with custom state tracked in the target’s MachineFunctionInfo? I’m trying to test a patch which checks a bit set in it during register allocation. If I just run the post-RA pass which checks it, it was never set in the newly constructed one. I’d rather not have every pass need to re-analyze some possibly tricky to detect situation to avoid using it -Matt
Alex L via llvm-dev
2016-Oct-13 09:34 UTC
[llvm-dev] Target MachineFunctionInfo and MIR passes
On 13 October 2016 at 09:19, Matt Arsenault via llvm-dev < llvm-dev at lists.llvm.org> wrote:> Hi, > > How are MIR passes supposed to deal with custom state tracked in the > target’s MachineFunctionInfo? I’m trying to test a patch which checks a bit > set in it during register allocation. If I just run the post-RA pass which > checks it, it was never set in the newly constructed one. I’d rather not > have every pass need to re-analyze some possibly tricky to detect situation > to avoid using it >Hi Matt, I haven't looked into MIR since last year, so maybe this has changed, but AFAIK there's no way to serialize target's custom machine function info state. I think I was working on patches that allowed targets to serialize custom machine function information using MIR before I finished my internship, so I'll try to dig them up again. Alex> > -Matt > _______________________________________________ > LLVM Developers mailing list > llvm-dev at lists.llvm.org > http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev >-------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20161013/4c944b28/attachment.html>