Alex Susu via llvm-dev
2016-Oct-10 18:54 UTC
[llvm-dev] Special vselect code generation case using TableGen
Hello. I addressed the problem in the end without using TableGen - in ISelLowering::LowerOperation(). It turned out that writing code to generate about 10 SDNode and especially linking them correctly is quite complicated (a few details at https://sites.google.com/site/alexsusu/home/backend-llvm, look for "P27. Making VSELECT instruction selection work"). I guess that one could do in TableGen, but I'm not very good at it and there are some difficulties: I need to create an SDNode of a certain target instruction depending on the predicate of the SETCC node being fed to the VSELECT. I would like to mention that an interesting example is given in the book Mayur Pandey, Suyog_Sarda, "LLVM Cookbook", 2015, page 226, section "Lowering to multiple instructions": it describes how we can do in InstrInfo correct instruction selection by first lowering a MOVi32 to MOVLOi16 and MOVHIi16 . Best regards, Alex> Could you do this in ISelLowering/DAGToDAG? This is probably where I would do this. I > think it would be cleaner there. > > On Oct 3, 2016 19:06, "Alex Susu via llvm-dev" <llvm-dev at lists.llvm.org > <mailto:llvm-dev at lists.llvm.org>> wrote: > > Hello. > I want to implement in TableGen code generation for vselect for the Connex > research SIMD processor. The problem is that my SIMD processor does not have a vselect > instruction and therefore we need to use the other existing instructions. More > exactly, if we have in LLVM IR a program like this: > %pred = cmp eq %op1, %op2 > %vres = vselect %pred, %if_set, %if_clear > we can implement it in Connex like this: > EQ op1, op2 > Rdst = Rif_clear > WHEREEQ > Rdst = Rif_set > ENDWHERE > > Normally TableGen allows specifying single instructions that match part of a given > DAG. > But in include/llvm/Target/TargetSelectionDAG.td it is given the possibility to > match a given DAG node with several target nodes by using Pattern<> records: > // Selection DAG Pattern Support. > // Patterns are what are actually matched against by the target-flavored > // instruction selection DAG. Instructions defined by the target implicitly > // define patterns in most cases, but patterns can also be explicitly added when > // an operation is defined by a sequence of instructions (e.g. loading a large > // immediate value on RISC targets that do not support immediates as large as > // their GPRs). > // > class Pattern<dag patternToMatch, list<dag> resultInstrs> { > dag PatternToMatch = patternToMatch; > list<dag> ResultInstrs = resultInstrs; > list<Predicate> Predicates = []; // See class Instruction in Target.td. > int AddedComplexity = 0; // See class Instruction in Target.td. > } > > // From MispMSAInstrInfo.td: (vselect cond, if_set, if_clear) > def : Pattern<(set MSA128BOpnd:$wd, (vselect (MSA128BOpnd:$pred), > (MSA128BOpnd:$ws_true), MSA128BOpnd:$ws_false)), > [ // assign value $ws_false to vregx, which keeps the result of > vselect - use CopyToReg > (WHEREEQ), // no inputs, no outputs > // assign value $ws_true to vregx, which keeps the result of > vselect - use CopyToReg > (ENDWHERE) // no inputs, no outputs > ] > >; > > I'm having difficulties in specifying this TableGen Pattern. > For example, does the "set" TableGen pattern operation specify CopyToReg? > > Thank you, > Alex > _______________________________________________ > LLVM Developers mailing list > llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org> > http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev > <http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev> >
Alex Susu via llvm-dev
2016-Oct-12 23:50 UTC
[llvm-dev] Special vselect code generation case using TableGen
Hello. I would like to ask a few more things related to the subject of manually generating SelectionDAG nodes (in C++, not with TableGen): - can I add new use edges to an already created node (that is the existing node to use some more values from some other node)? - is it OK to add a chain or glue edge between a node with a chain/glue output and a node that has no chain/glue input? - is it OK to add a chain or glue output to a machine instruction defined in TableGen that does not have any output? Thank you, Alex On 10/10/2016 9:54 PM, Alex Susu wrote:> Hello. > I addressed the problem in the end without using TableGen - in > ISelLowering::LowerOperation(). It turned out that writing code to generate about 10 > SDNode and especially linking them correctly is quite complicated (a few details at > https://sites.google.com/site/alexsusu/home/backend-llvm, look for "P27. Making VSELECT > instruction selection work"). > I guess that one could do in TableGen, but I'm not very good at it and there are some > difficulties: I need to create an SDNode of a certain target instruction depending on the > predicate of the SETCC node being fed to the VSELECT. > > I would like to mention that an interesting example is given in the book Mayur Pandey, > Suyog_Sarda, "LLVM Cookbook", 2015, page 226, section "Lowering to multiple instructions": > it describes how we can do in InstrInfo correct instruction selection by first lowering a > MOVi32 to MOVLOi16 and MOVHIi16 . > > Best regards, > Alex > > >> Could you do this in ISelLowering/DAGToDAG? This is probably where I would do this. I >> think it would be cleaner there. >> >> On Oct 3, 2016 19:06, "Alex Susu via llvm-dev" <llvm-dev at lists.llvm.org >> <mailto:llvm-dev at lists.llvm.org>> wrote: >> >> Hello. >> I want to implement in TableGen code generation for vselect for the Connex >> research SIMD processor. The problem is that my SIMD processor does not have a vselect >> instruction and therefore we need to use the other existing instructions. More >> exactly, if we have in LLVM IR a program like this: >> %pred = cmp eq %op1, %op2 >> %vres = vselect %pred, %if_set, %if_clear >> we can implement it in Connex like this: >> EQ op1, op2 >> Rdst = Rif_clear >> WHEREEQ >> Rdst = Rif_set >> ENDWHERE >> >> Normally TableGen allows specifying single instructions that match part of a given >> DAG. >> But in include/llvm/Target/TargetSelectionDAG.td it is given the possibility to >> match a given DAG node with several target nodes by using Pattern<> records: >> // Selection DAG Pattern Support. >> // Patterns are what are actually matched against by the target-flavored >> // instruction selection DAG. Instructions defined by the target implicitly >> // define patterns in most cases, but patterns can also be explicitly added when >> // an operation is defined by a sequence of instructions (e.g. loading a large >> // immediate value on RISC targets that do not support immediates as large as >> // their GPRs). >> // >> class Pattern<dag patternToMatch, list<dag> resultInstrs> { >> dag PatternToMatch = patternToMatch; >> list<dag> ResultInstrs = resultInstrs; >> list<Predicate> Predicates = []; // See class Instruction in Target.td. >> int AddedComplexity = 0; // See class Instruction in Target.td. >> } >> >> // From MispMSAInstrInfo.td: (vselect cond, if_set, if_clear) >> def : Pattern<(set MSA128BOpnd:$wd, (vselect (MSA128BOpnd:$pred), >> (MSA128BOpnd:$ws_true), MSA128BOpnd:$ws_false)), >> [ // assign value $ws_false to vregx, which keeps the result of >> vselect - use CopyToReg >> (WHEREEQ), // no inputs, no outputs >> // assign value $ws_true to vregx, which keeps the result of >> vselect - use CopyToReg >> (ENDWHERE) // no inputs, no outputs >> ] >> >; >> >> I'm having difficulties in specifying this TableGen Pattern. >> For example, does the "set" TableGen pattern operation specify CopyToReg? >> >> Thank you, >> Alex >> _______________________________________________ >> LLVM Developers mailing list >> llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org> >> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev >> <http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev> >>