Rail Shafigulin via llvm-dev
2016-Feb-04 19:41 UTC
[llvm-dev] New register class and patterns
It does have an output register, it's just an implicit flag register. It still has a DAG output. I'm not sure if the allocatable bit matters at this point for selection purposes, but it does later. Not adding a type to the register class can also be problematic (e.g. a flag register should have i1 added to regTypes for its class). -Matt>Does LLVM make an assumption that there is an implicit register output if there are no outputs given to the pattern? I'm also curious about how did LLVM know that an output of this instruction was setting a flag in a special purpose register rather than a GPR? When I look at the DAG pattern for the instruction, (Escalasetflag (i32 GPR:$rA), immSExt16:$imm, Cond), I can't find anything saying that it sets a flag in the special purpose register. I'm reposting code for convenience. def SDT_EscalaSetFlag : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>]>; def Escalatflag : SDNode<"EscalaISD::SET_FLAG", SDT_EscalaSetFlag, [SDNPOutGlue]>; def Escala_CC_EQ : PatLeaf<(imm), [{return (N->getZExtValue() == ISD::SETEQ);}]>; class SF_RI<bits<5> op2Val, string asmstr, PatLeaf Cond> : InstRI<0xf, (outs), (ins GPR:$rA, s16imm:$imm), !strconcat(asmstr, "i\t$rA, $imm"), [(Escalasetflag (i32 GPR:$rA), immSExt16:$imm, Cond)]> { bits<5> op2; bits<5> rA; bits<16> imm; let Inst{25-21} = op2; let Inst{20-16} = rA; let Inst{15-0} = imm; let format = AFrm; let op2 = op2Val; } multiclass SF<bits<5> op2Val, string asmstr, PatLeaf Cond> { def _rr : SF_RR<op2Val, asmstr, Cond>; def _ri : SF_RI<op2Val, asmstr, Cond>; } defm SFEQ : SF<0x0, "l.sfeq", Escala_CC_EQ>; -- Rail Shafigulin Software Engineer Esencia Technologies -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160204/dcf1e383/attachment-0001.html>
Matt Arsenault via llvm-dev
2016-Feb-05 19:21 UTC
[llvm-dev] New register class and patterns
On 02/04/2016 11:41 AM, Rail Shafigulin wrote:> Does LLVM make an assumption that there is an implicit register output > if there are no outputs given to the pattern? I'm also curious about > how did LLVM know that an output of this instruction was setting a > flag in a special purpose register rather than a GPR? When I look at > the DAG pattern for the instruction, (Escalasetflag (i32 GPR:$rA), > immSExt16:$imm, Cond), I can't find anything saying that it sets a > flag in the special purpose register.No, this would have to be a void side effecting instruction which is a bit different. The flag register is an implicit register added to the selected MachineInstr's operands. -Matt
Rail Shafigulin via llvm-dev
2016-Feb-05 20:00 UTC
[llvm-dev] New register class and patterns
> > No, this would have to be a void side effecting instruction which is a bit > different.What do you mean by "void side effecting instruction"? I'm not sure I fully understand what you mean. The flag register is an implicit register added to the selected> MachineInstr's operands.Is this something that is always done by LLVM? Is it me who is telling to LLVM to do it? I'd appreciate if you could point out where in the code this is happening. I've also followed your advice and added i1 as a type for my SPR def SPR : RegisterClass<"Esencia", [i1,i32], 32, (add SR)> { let CopyCost = -1; // Don't allow copying of special purpose registers. let isAllocatable = 0; } Then I changed an instruction class to return an explicit value class SF_RR<bits<5> op2Val, string asmstr, PatLeaf Cond> : InstRR<0x9, (outs), (ins GPR:$rA, GPR:$rB), !strconcat(asmstr, "\t$rA, $rB"), [(set SPR:$rC, (Esenciasetflag (i32 GPR:$rA), (i32 GPR:$rB), Cond))]> { bits<5> op2; bits<5> rA; bits<5> rB; let Inst{25-21} = op2; let Inst{20-16} = rA; let Inst{15-11} = rB; let op2 = op2Val; } Naturally LLVM didn't like it. I'm getting stack dumps when I compile it. I'm assuming this is happening because LLVM is not expecting to see an explicit output. As far as I understand my options are: 1. Have an instruction return an explicit value, but then I will have to do a lot of work to change a large chunk of the backend. 2. Continue working with an implicit value being set by an instruction. I'd like to introduce as little changes as I can. So option 2 seems to be a reasonable one, however I can't figure out where and what I need to change. As most people on this list, I'm also learning "on the fly" I'd really appreciate any help on this. -- Rail Shafigulin Software Engineer Esencia Technologies -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160205/ecfda8ba/attachment.html>