llvm dev - Sep 2015 - Register Number

Dear all,

in my TestRegisterInfo.td file, I defined a register like this:

class TestReg<bits<6> enc, string name> : Register<name> {
  let HWEncoding{5-0} = enc;
  let Namespace = "TEST";
}

def D0   : TestReg<0x01,   "d0">, DwarfRegNum<[1]>;

but when I compile, the result I have in TestGenAsmMatcher.inc is this:

case 'd':    // 7 strings to match.
  switch (Name[1]) {
      case '0':  // 1 string to match.
        return* 14*;       // "d0"

I supposed I will get either 1 (because of encoding) or 0 (because of
DwarfRegNum). Is this 14 something system generated? How can I assign my
own number to the registers?

Cheers,
ES
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It seems like d0 is always 14!
I check it with ARMGenAsmMatcher.inc it was the same!
How is it possible? because it should give the same register value that
matches the underlying platform not any autogenerated value!?

On Thu, Sep 17, 2015 at 10:26 AM, Sky Flyer <skylake007 at googlemail.com>
wrote:
> Dear all,
>
> in my TestRegisterInfo.td file, I defined a register like this:
>
> class TestReg<bits<6> enc, string name> : Register<name>
{
>   let HWEncoding{5-0} = enc;
>   let Namespace = "TEST";
> }
>
> def D0   : TestReg<0x01,   "d0">, DwarfRegNum<[1]>;
>
> but when I compile, the result I have in TestGenAsmMatcher.inc is this:
>
> case 'd':    // 7 strings to match.
>   switch (Name[1]) {
>       case '0':  // 1 string to match.
>         return* 14*;       // "d0"
>
> I supposed I will get either 1 (because of encoding) or 0 (because of
> DwarfRegNum). Is this 14 something system generated? How can I assign my
> own number to the registers?
>
> Cheers,
> ES
>
>
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On 9/17/2015 7:04 AM, Sky Flyer via llvm-dev wrote:
> It seems like d0 is always 14!
> I check it with ARMGenAsmMatcher.inc it was the same!
> How is it possible? because it should give the same register value that
> matches the underlying platform not any autogenerated value!?
The returned number is the register id as defined in 
<YourTarget>GenRegisterInfo.inc.  These numbers don't have any meaning
other than to represent a particular register.  The 0x01 would be the 
encoding used in generating the binary.

The D0 has id 14 on ARM because there are 13 other registers preceding it:
namespace ARM {
enum {
   NoRegister,
   APSR = 1,
   APSR_NZCV = 2,
   CPSR = 3,
   FPEXC = 4,
   FPINST = 5,
   FPSCR = 6,
   FPSCR_NZCV = 7,
   FPSID = 8,
   ITSTATE = 9,
   LR = 10,
   PC = 11,
   SP = 12,
   SPSR = 13,
   D0 = 14,
   ...

-Krzysztof

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