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hamza halli

2015-Jun-08 20:42 UTC

[LLVMdev] Adjusting Instruction Latencies

Hello,
I’m working on a custom instruction scheduling for a modified ARMv7A
architecture. I’m trying to set manually the instruction latencies for this
target without overwriting the pipeline itineraries by writing -for example- the
following code in armbaseinstrinfo.cpp.
By doing this I still get the default instruction latencies of the ARMv7 when I
run my custom scheduler.
Can somebody please help me on this matter?
Thanks

unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
                                           const MachineInstr *MI,
                                           unsigned *PredCost) const {
    

      
    switch (MI->getOpcode()) {

        case ARM::ANDri:
        case ARM::ANDrr:
        case ARM::ANDrsi:
        case ARM::ANDrsr:
        case ARM::EORri:
        case ARM::EORrr:
        case ARM::EORrsi:
        case ARM::EORrsr:
        case ARM::ORRri:
        case ARM::ORRrr:
        case ARM::ORRrsi:
        case ARM::ORRrsr:
            return 1;
            break;
  

        case ARM::LSLi:
        case ARM::LSLr:
        case ARM::LSRi:
        case ARM::LSRr:
        case ARM::ADDri:
        case ARM::ADDrr:
        case ARM::ADCrsi:
        case ARM::ADCrsr:
        case ARM::ADCri:
        case ARM::ADCrr:
        case ARM::ADDrsi:
        case ARM::ADDrsr:
        case ARM::ADDSri:
        case ARM::ADDSrr:
        case ARM::ADDSrsi:
        case ARM::ADDSrsr:
        case ARM::ASRi:
        case ARM::ASRr:
        case ARM::CMNri:
        case ARM::CMNzrr:
        case ARM::CMNzrsi:
        case ARM::CMNzrsr:
        case ARM::CMPri:
        case ARM::CMPrr:
        case ARM::CMPrsi:
        case ARM::CMPrsr:
        case ARM::QADD:
        case ARM::QADD16:
        case ARM::QADD8:
        case ARM::QASX:
        case ARM::QDADD:
        case ARM::QDSUB:
        case ARM::QSAX:
        case ARM::QSUB:
        case ARM::QSUB16:
        case ARM::QSUB8:
        case ARM::RORi:
        case ARM::RORr:
        case ARM::RRX:
        case ARM::RRXi:
        case ARM::RSBri:
        case ARM::RSBrr:
        case ARM::RSBrsi:
        case ARM::RSBrsr:
        case ARM::RSBSri:
        case ARM::RSBSrsi:
        case ARM::RSBSrsr:
        case ARM::RSCri:
        case ARM::RSCrr:
        case ARM::RSCrsi:
        case ARM::RSCrsr:
        case ARM::SADD16:
        case ARM::SADD8:
        case ARM::SASX:
        case ARM::SBCri:
        case ARM::SBCrr:
        case ARM::SBCrsi:
        case ARM::SBCrsr:
        case ARM::SBFX:
        case ARM::SEL:
        case ARM::SETEND:
            
            
        case ARM::SSAT:
        case ARM::SSAT16:
        case ARM::SSAX:
        case ARM::SSUB16:
        case ARM::SSUB8:
        case ARM::SUBri:
        case ARM::SUBrr:
        case ARM::SUBrsi:
        case ARM::SUBrsr:
        case ARM::SUBS_PC_LR:
        case ARM::SUBSri:
        case ARM::SUBSrr:
        case ARM::SUBSrsi:
        case ARM::SUBSrsr:
        case ARM::SWP:
        case ARM::SWPB:
        case ARM::SXTAB:
        case ARM::SXTAB16:
        case ARM::SXTAH:
        case ARM::SXTB:
        case ARM::SXTB16:
        case ARM::SXTH:
        case ARM::TEQri:
        case ARM::TEQrr:
        case ARM::TEQrsi:
        case ARM::TEQrsr:
        case ARM::TSTri:
        case ARM::TSTrr:
        case ARM::TSTrsi:
        case ARM::TSTrsr:
        case ARM::UADD16:
        case ARM::UADD8:
        case ARM::UASX:
        case ARM::UBFX:
        case ARM::UHADD16:
        case ARM::UHADD8:
        case ARM::UHASX:
        case ARM::UHSAX:
        case ARM::UHSUB16:
        case ARM::UHSUB8:
        case ARM::UQADD16:
        case ARM::UQADD8:
        case ARM::UQASX:
        case ARM::UQSAX:
        case ARM::UQSUB16:
        case ARM::UQSUB8:
        case ARM::USAD8:
        case ARM::USADA8:
        case ARM::USAT:
        case ARM::USAT16:
        case ARM::USAX:
        case ARM::USUB16:
        case ARM::USUB8:
        case ARM::UXTAB:
        case ARM::UXTAB16:
        case ARM::UXTAH:
        case ARM::UXTB:
        case ARM::UXTB16:
        case ARM::UXTH:
            return 2;
            break;




        case ARM::MLA:
        case ARM::MLAv5:
        case ARM::MLS:
        case ARM::MUL:
        case ARM::MULv5:
        case ARM::SDIV:
            
        case ARM::SMLABB:
        case ARM::SMLABT:
        case ARM::SMLAD:
        case ARM::SMLADX:
        case ARM::SMLAL:
        case ARM::SMLALBB:
        case ARM::SMLALBT:
        case ARM::SMLALD:
        case ARM::SMLALDX:
        case ARM::SMLALTB:
        case ARM::SMLALTT:
        case ARM::SMLALv5:
        case ARM::SMLATB:
        case ARM::SMLATT:
        case ARM::SMLAWB:
        case ARM::SMLAWT:
        case ARM::SMLSD:
        case ARM::SMLSDX:
        case ARM::SMLSLD:
        case ARM::SMLSLDX:
        case ARM::SMMLA:
        case ARM::SMMLAR:
        case ARM::SMMLS:
        case ARM::SMMLSR:
        case ARM::SMMUL:
        case ARM::SMMULR:
        case ARM::SMUAD:
        case ARM::SMUADX:
        case ARM::SMULBB:
        case ARM::SMULBT:
        case ARM::SMULL:
        case ARM::SMULLv5:
        case ARM::SMULTB:
        case ARM::SMULTT:
        case ARM::SMULWB:
        case ARM::SMULWT:
        case ARM::SMUSD:
        case ARM::SMUSDX:
        case ARM::UMAAL:
        case ARM::UMLAL:
        case ARM::UMLALv5:
        case ARM::UMULL:
        case ARM::UMULLv5:
        case ARM::UDIV:
            return 6;
            break;
            

            
        case ARM::STC2_OFFSET:
        case ARM::STC2_OPTION:
        case ARM::STC2_POST:
        case ARM::STC2_PRE:
        case ARM::STC2L_OFFSET:
        case ARM::STC2L_OPTION:
        case ARM::STC2L_PRE:
        case ARM::STC_OFFSET:
        case ARM::STC_OPTION:
        case ARM::STC_POST:
        case ARM::STC_PRE:
        case ARM::STCL_OFFSET:
        case ARM::STCL_OPTION:
        case ARM::STCL_POST:
        case ARM::STCL_PRE:
        case ARM::STL:
        case ARM::STLB:
        case ARM::STLEX:
        case ARM::STLEXB:
        case ARM::STLEXD:
        case ARM::STLEXH:
        case ARM::STLH:
        case ARM::STMDA:
        case ARM::STMDA_UPD:
        case ARM::STMDB:
        case ARM::STMDB_UPD:
        case ARM::STMIA:
        case ARM::STMIA_UPD:
        case ARM::STMIB:
        case ARM::STMIB_UPD:
        case ARM::STR_POST_IMM:
        case ARM::STR_POST_REG:
        case ARM::STR_PRE_IMM:
        case ARM::STR_PRE_REG:
        case ARM::STRB_POST_IMM:
        case ARM::STRB_POST_REG:
        case ARM::STRB_PRE_IMM:
        case ARM::STRB_PRE_REG:
        case ARM::STRBi12:
        case ARM::STRBi_preidx:
        case ARM::STRBr_preidx:
        case ARM::STRBrs:
        case ARM::STRBT_POST:
        case ARM::STRBT_POST_IMM:
        case ARM::STRBT_POST_REG:
        case ARM::STRD:
        case ARM::STRD_POST:
        case ARM::STRD_PRE:
        case ARM::STREX:
        case ARM::STREXB:
        case ARM::STREXD:
        case ARM::STREXH:
        case ARM::STRH:
        case ARM::STRH_POST:
        case ARM::STRH_PRE:
        case ARM::STRH_preidx:
        case ARM::STRHTi:
        case ARM::STRHTr:
        case ARM::STRi12:
        case ARM::STRi_preidx:
        case ARM::STRr_preidx:
        case ARM::STRrs:
        case ARM::STRT_POST:
        case ARM::STRT_POST_IMM:
        case ARM::STRT_POST_REG:
            return 6;
            break;
            

            
        case ARM::LDA:
        case ARM::LDAB:
        case ARM::LDAEX:
        case ARM::LDAEXB:
        case ARM::LDAEXD:
        case ARM::LDAEXH:
        case ARM::LDAH:
        case ARM::LDC2_OFFSET:
        case ARM::LDC2_OPTION:
        case ARM::LDC2_POST:
        case ARM::LDC2_PRE:
        case ARM::LDC2L_OFFSET:
        case ARM::LDC2L_OPTION:
        case ARM::LDC2L_POST:
        case ARM::LDC2L_PRE:
        case ARM::LDC_OFFSET:
        case ARM::LDC_OPTION:
        case ARM::LDC_POST:
        case ARM::LDC_PRE:
        case ARM::LDCL_OFFSET:
        case ARM::LDCL_OPTION:
        case ARM::LDCL_POST:
        case ARM::LDCL_PRE:
        case ARM::LDMDA:
        case ARM::LDMDA_UPD:
        case ARM::LDMDB:
            
        case ARM::LDMDB_UPD:
        case ARM::LDMIA:
        case ARM::LDMIA_RET:
        case ARM::LDMIA_UPD:
        case ARM::LDMIB:
        case ARM::LDMIB_UPD:
        case ARM::LDR_POST_IMM:
        case ARM::LDR_POST_REG:
        case ARM::LDR_PRE_IMM:
        case ARM::LDR_PRE_REG:
        case ARM::LDRB_POST_IMM:
        case ARM::LDRB_POST_REG:
        case ARM::LDRB_PRE_IMM:
        case ARM::LDRB_PRE_REG:
        case ARM::LDRBi12:
        case ARM::LDRBrs:
        case ARM::LDRBT_POST:
        case ARM::LDRBT_POST_IMM:
        case ARM::LDRBT_POST_REG:
        case ARM::LDRcp:
        case ARM::LDRD:
        case ARM::LDRD_POST:
        case ARM::LDRD_PRE:
        case ARM::LDREX:
        case ARM::LDREXB:
        case ARM::LDREXD:
        case ARM::LDREXH:
        case ARM::LDRH:
        case ARM::LDRH_POST:
        case ARM::LDRH_PRE:
        case ARM::LDRHTi:
        case ARM::LDRHTr:
        case ARM::LDRi12:
        case ARM::LDRLIT_ga_abs:
        case ARM::LDRLIT_ga_pcrel:
        case ARM::LDRLIT_ga_pcrel_ldr:
        case ARM::LDRrs:
        case ARM::LDRSB:
        case ARM::LDRSB_POST:
        case ARM::LDRSB_PRE:
        case ARM::LDRSBTi:
        case ARM::LDRSBTr:
        case ARM::LDRSH:
        case ARM::LDRSH_POST:
        case ARM::LDRSH_PRE:
        case ARM::LDRSHTi:
        case ARM::LDRSHTr:
        case ARM::LDRT_POST:
        case ARM::LDRT_POST_IMM:
        case ARM::LDRT_POST_REG:
   
            return 8;
            break;
            
        default:
            
            break;
    }
    



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hamza halli

2015-Jun-09 17:43 UTC

head link

[LLVMdev] Adjusting Instruction Latencies

> 
> 
> Hello,
> I’m working on a custom instruction scheduling for a modified ARMv7A
architecture. I’m trying to set manually the instruction latencies for this
target without overwriting the pipeline itineraries by writing -for example- the
following code in armbaseinstrinfo.cpp.
> By doing this I still get the default instruction latencies of the ARMv7
when I run my custom scheduler.
> Can somebody please help me on this matter?
> Thanks
> 
> unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData
*ItinData,
>                                            const MachineInstr *MI,
>                                            unsigned *PredCost) const {
>     
> 
>       
>     switch (MI->getOpcode()) {
> 
>         case ARM::ANDri:
>         case ARM::ANDrr:
>         case ARM::ANDrsi:
>         case ARM::ANDrsr:
>         case ARM::EORri:
>         case ARM::EORrr:
>         case ARM::EORrsi:
>         case ARM::EORrsr:
>         case ARM::ORRri:
>         case ARM::ORRrr:
>         case ARM::ORRrsi:
>         case ARM::ORRrsr:
>             return 1;
>             break;
>   
> 
>         case ARM::LSLi:
>         case ARM::LSLr:
>         case ARM::LSRi:
>         case ARM::LSRr:
>         case ARM::ADDri:
>         case ARM::ADDrr:
>         case ARM::ADCrsi:
>         case ARM::ADCrsr:
>         case ARM::ADCri:
>         case ARM::ADCrr:
>         case ARM::ADDrsi:
>         case ARM::ADDrsr:
>         case ARM::ADDSri:
>         case ARM::ADDSrr:
>         case ARM::ADDSrsi:
>         case ARM::ADDSrsr:
>         case ARM::ASRi:
>         case ARM::ASRr:
>         case ARM::CMNri:
>         case ARM::CMNzrr:
>         case ARM::CMNzrsi:
>         case ARM::CMNzrsr:
>         case ARM::CMPri:
>         case ARM::CMPrr:
>         case ARM::CMPrsi:
>         case ARM::CMPrsr:
>         case ARM::QADD:
>         case ARM::QADD16:
>         case ARM::QADD8:
>         case ARM::QASX:
>         case ARM::QDADD:
>         case ARM::QDSUB:
>         case ARM::QSAX:
>         case ARM::QSUB:
>         case ARM::QSUB16:
>         case ARM::QSUB8:
>         case ARM::RORi:
>         case ARM::RORr:
>         case ARM::RRX:
>         case ARM::RRXi:
>         case ARM::RSBri:
>         case ARM::RSBrr:
>         case ARM::RSBrsi:
>         case ARM::RSBrsr:
>         case ARM::RSBSri:
>         case ARM::RSBSrsi:
>         case ARM::RSBSrsr:
>         case ARM::RSCri:
>         case ARM::RSCrr:
>         case ARM::RSCrsi:
>         case ARM::RSCrsr:
>         case ARM::SADD16:
>         case ARM::SADD8:
>         case ARM::SASX:
>         case ARM::SBCri:
>         case ARM::SBCrr:
>         case ARM::SBCrsi:
>         case ARM::SBCrsr:
>         case ARM::SBFX:
>         case ARM::SEL:
>         case ARM::SETEND:
>             
>             
>         case ARM::SSAT:
>         case ARM::SSAT16:
>         case ARM::SSAX:
>         case ARM::SSUB16:
>         case ARM::SSUB8:
>         case ARM::SUBri:
>         case ARM::SUBrr:
>         case ARM::SUBrsi:
>         case ARM::SUBrsr:
>         case ARM::SUBS_PC_LR:
>         case ARM::SUBSri:
>         case ARM::SUBSrr:
>         case ARM::SUBSrsi:
>         case ARM::SUBSrsr:
>         case ARM::SWP:
>         case ARM::SWPB:
>         case ARM::SXTAB:
>         case ARM::SXTAB16:
>         case ARM::SXTAH:
>         case ARM::SXTB:
>         case ARM::SXTB16:
>         case ARM::SXTH:
>         case ARM::TEQri:
>         case ARM::TEQrr:
>         case ARM::TEQrsi:
>         case ARM::TEQrsr:
>         case ARM::TSTri:
>         case ARM::TSTrr:
>         case ARM::TSTrsi:
>         case ARM::TSTrsr:
>         case ARM::UADD16:
>         case ARM::UADD8:
>         case ARM::UASX:
>         case ARM::UBFX:
>         case ARM::UHADD16:
>         case ARM::UHADD8:
>         case ARM::UHASX:
>         case ARM::UHSAX:
>         case ARM::UHSUB16:
>         case ARM::UHSUB8:
>         case ARM::UQADD16:
>         case ARM::UQADD8:
>         case ARM::UQASX:
>         case ARM::UQSAX:
>         case ARM::UQSUB16:
>         case ARM::UQSUB8:
>         case ARM::USAD8:
>         case ARM::USADA8:
>         case ARM::USAT:
>         case ARM::USAT16:
>         case ARM::USAX:
>         case ARM::USUB16:
>         case ARM::USUB8:
>         case ARM::UXTAB:
>         case ARM::UXTAB16:
>         case ARM::UXTAH:
>         case ARM::UXTB:
>         case ARM::UXTB16:
>         case ARM::UXTH:
>             return 2;
>             break;
> 
> 		
				 > 
> 
>         case ARM::LDRLIT_ga_pcrel_ldr:
>         case ARM::LDRrs:
>         case ARM::LDRSB:
>         case ARM::LDRSB_POST:
>         case ARM::LDRSB_PRE:
>         case ARM::LDRSBTi:
>         case ARM::LDRSBTr:
>         case ARM::LDRSH:
>         case ARM::LDRSH_POST:
>         case ARM::LDRSH_PRE:
>         case ARM::LDRSHTi:
>         case ARM::LDRSHTr:
>         case ARM::LDRT_POST:
>         case ARM::LDRT_POST_IMM:
>         case ARM::LDRT_POST_REG:
>    
>             return 8;
>             break;
>             
>         default:
>             
>             break;
>     }
>     
> 
> 
> 
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llvm dev - Jun 2015 - [LLVMdev] Adjusting Instruction Latencies

[LLVMdev] Adjusting Instruction Latencies

[LLVMdev] Adjusting Instruction Latencies