Alex L
2015-Apr-28 17:46 UTC
[LLVMdev] RFC: Machine Level IR text-based serialization format
2015-04-28 10:09 GMT-07:00 Krzysztof Parzyszek <kparzysz at codeaurora.org>:> Looks good. How are you planning to "assemble" the MI-level YAML > description into the actual in-memory IR?I plan on developing a parser for the new text format for the machine instructions. This parser will parse instructions, operands and memory operands, and it will after run the machine function and the embedded LLVM IR are parsed, so that the references to the basic blocks, constant pools, frame indices, etc. can be resolved immediately. Each string literal in a list of instructions in a machine basic blocks will be parsed using this parser and then they will be assembled together into a list of instructions for that basic block. I hope that answers your question, Alex.> > > -Krzysztof > > -- > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted > by The Linux Foundation > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev >-------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20150428/0446bb66/attachment.html>
Krzysztof Parzyszek
2015-Apr-28 17:52 UTC
[LLVMdev] RFC: Machine Level IR text-based serialization format
On 4/28/2015 12:46 PM, Alex L wrote:> > I hope that answers your question,Partly. :) I'm wondering what support you would need from each target. Obviously you'd need to be able to parse the mnemonics and the register names, but that's probably doable without additional target-specific support. Also, is this going to support SSA and post-SSA/post-RA code? -Krzysztof -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Alex L
2015-Apr-28 18:35 UTC
[LLVMdev] RFC: Machine Level IR text-based serialization format
2015-04-28 10:52 GMT-07:00 Krzysztof Parzyszek <kparzysz at codeaurora.org>:> On 4/28/2015 12:46 PM, Alex L wrote: > >> >> I hope that answers your question, >> > > Partly. :) > I'm wondering what support you would need from each target. Obviously > you'd need to be able to parse the mnemonics and the register names, but > that's probably doable without additional target-specific support. >Yes, the mnemonics and register names should be fairly straight forward. However, there are several target specific data structures that a machine function might have, like the MachineFunctionInfo. The MachineFunctionInfo is particularly interesting, as it can be difficult to serialize on certain targets, like Mips, XCore and Hexagon, but luckily the other targets have a pretty simple subclass of MachineFunctionInfo. I think that each target's MachineFunctionInfo and other similar classes would have to be extended to contain the intrusive methods for serialization. The instructions themselves don't have too many target specific stuff, but they do have a couple of things. Although there are some target specific things that don't even need to be serialized - like the MipsCallEntry, which can be used in a MachineMemOperand, but doesn't contain any data when LLVM is compiled in release mode. Alex.> Also, is this going to support SSA and post-SSA/post-RA code?Yes, it's going to support both SSA and post SSA code.> > > -Krzysztof > > -- > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted > by The Linux Foundation >-------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20150428/a22ae4b9/attachment.html>