Thanks Kevin for the reply. I got the point now :) On 10 Apr 2015 00:18, "Smith, Kevin B" <kevin.b.smith at intel.com> wrote:> For x86_64 ABI, a minimum feature set of SSE2 is required. > > > > Kevin > > > > *From:* llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] *On > Behalf Of *suyog sarda > *Sent:* Thursday, April 09, 2015 11:27 AM > *To:* LLVM Developers Mailing List; David Majnemer; Sanjay Patel > *Subject:* [LLVMdev] MMX/SSE subtarget feature in IR > > > > Hi all, > > > > I have a sample test case : > > > > $ cat 1.c > > > > int foo(int x, int y){ > > int z = x + y; > > return z/2; > > } > > > > I tried to get its IR form with clang providing subtarget feature as mmx > for target x86_64 > > > > $ clang -O3 -mmmx 1.c -S -emit-llvm > > > > in the IR generated i can see the subtarget-features as function attribute > : > > > > "target-features"="+mmx" > > > > In the SelectionDAG phase in file "X86ISelLowering.cpp", i checked in one > of the function what is the subtarget feature by calling few routines of > Subtarget. > > > > Subtarget->hasMMX() ------ true > > Subtarget->hasSSE1() ------ true > > Subtarget->hasSSE2() ------ true > > > > These functions just compare the X86SSELevel with subtarget enum values > like MMX, SSE1, SSE2 etc. > > > > hasMMX() { return X86SSELevel >= MMX}; // similar for others > > > > Now, enum values start from MMX and goes on increasing with SSE1, SSE2, > etc. > > > > For the above test case, the X86SSELevel is set to SSE2, which is > confusing, since i have explicitly specified the target feature as 'mmx'. > Why the X86SSELevel is getting set to SSE2 despite providing target-feature > as mmx? Is it something to do with default feature of x86_64? > > > > I wanted to distinguish my code generation based on subtarget feature for > MMX and SSE, which i am unable to do so currently because of above scenario. > > > > I am sure i am missing something fundamental, but unable to exactly find > out what. > > > > Can someone please help me out on above question? > > > > Thanks. > > > > Regards, > > Suyog Sarda >-------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20150410/cfdb53c4/attachment.html>
Hi Kevin, I had another query for 32 bit x86. (Apology for being naive) I guess the default CPU on 32-bit x86 is 'pentium4', which has SSE as seen in getX86TargetCPU() in tools/clang/lib/Driver/Tools.cpp: static const char *getX86TargetCPU(const ArgList &Args, const llvm::Triple &Triple) { ... // Everything else goes to x86-64 in 64-bit mode. if (Is64Bit) return "x86-64"; switch (Triple.getOS()) { case llvm::Triple::FreeBSD: case llvm::Triple::NetBSD: case llvm::Triple::OpenBSD: return "i486"; case llvm::Triple::Haiku: return "i586"; case llvm::Triple::Bitrig: return "i686"; default: // Fallback to p4. return "pentium4"; } } Is there any 32-bit CPU with MMX feature but without SSE feature? Can it be done as follows : $ clang 1.c -mmmx -mno-sse -emit-llvm -S -target i386. My intention is to generate IR for x86 32 bit CPU with MMX feature but without SSE feature and further investigate if vectorization triggers for 32 bit architecture with MMX feature only. Thanks. Regards, Suyog Sarda -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20150410/675e171f/attachment.html>
Your clang invocation below works for me, and generates target triple in the llvm IR of i386. And then in the specific options for the functions it generates the following: ; Function Attrs: nounwind define float @foo() #0 { entry: ret float 1.000000e+00 } attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim""true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-ma th"="false" "stack-protector-buffer-size"="8" "target-cpu"="pentium4" "target-fe atures"="+mmx,-sse" "unsafe-fp-math"="false" "use-soft-float"="false" } The attributes indicate to allow mmx, disallow sse, so this certainly looks like it might work. I don't know whether work has been done to specifically do something special for this combination, since use of MMX overlaps with X87 floating point state. The processors that support mmx, but not SSE would be Pentium w MMX processor Pentium II family processors Kevin From: suyog sarda [mailto:sardask01 at gmail.com] Sent: Friday, April 10, 2015 2:51 AM To: Smith, Kevin B Cc: Sanjay Patel; David Majnemer; LLVM Developers Mailing List Subject: Re: [LLVMdev] MMX/SSE subtarget feature in IR Hi Kevin, I had another query for 32 bit x86. (Apology for being naive) I guess the default CPU on 32-bit x86 is 'pentium4', which has SSE as seen in getX86TargetCPU() in tools/clang/lib/Driver/Tools.cpp: static const char *getX86TargetCPU(const ArgList &Args, const llvm::Triple &Triple) { ... // Everything else goes to x86-64 in 64-bit mode. if (Is64Bit) return "x86-64"; switch (Triple.getOS()) { case llvm::Triple::FreeBSD: case llvm::Triple::NetBSD: case llvm::Triple::OpenBSD: return "i486"; case llvm::Triple::Haiku: return "i586"; case llvm::Triple::Bitrig: return "i686"; default: // Fallback to p4. return "pentium4"; } } Is there any 32-bit CPU with MMX feature but without SSE feature? Can it be done as follows : $ clang 1.c -mmmx -mno-sse -emit-llvm -S -target i386. My intention is to generate IR for x86 32 bit CPU with MMX feature but without SSE feature and further investigate if vectorization triggers for 32 bit architecture with MMX feature only. Thanks. Regards, Suyog Sarda -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20150410/dfddbcb6/attachment.html>