Dave Pitsbawn
2015-Apr-06 03:54 UTC
[LLVMdev] Unreachable br in IR but still seems to be executed
I'm trying to implement a continue statement like in C if (i % 2 == 0) { i = i + 1; continue; } else { i = i + 1; } My code generates IR like this, because of how I visit my AST, so when I encounter a continue or break statement I go and find the corresponding while. I was hoping LLVM would do the right thing which is ignore the unreachable IR (br label %if.end). But it seems to somehow get to execute statements after my br I've marked it with "SHOULD NOT HAPPEN" define i32 @Main() { entry: %i = alloca i32 %loopCounter = alloca i32 store i32 0, i32* %i store i32 0, i32* %loopCounter br label %while.cond while.cond: ; preds = %if.end, %if.then, % entry %0 = load i32* %i %cmptmp = icmp slt i32 %0, 100 br i1 %cmptmp, label %while.body, label %while.end while.body: ; preds = %while.cond %1 = load i32* %i %modtmp = srem i32 %1, 2 %cmptmp1 = icmp eq i32 %modtmp, 0 br i1 %cmptmp1, label %if.then, label %if.else while.end: ; preds = %while.cond %2 = load i32* %loopCounter ret i32 %2 if.then: ; preds = %while.body %3 = load i32* %i %add = add i32 %3, 1 store i32 %add, i32* %i br label %while.cond %4 = load i32* %I <----------- SHOULD NOT HAPPEN %sub = sub i32 %4, 1 store i32 %sub, i32* %i br label %if.end if.else: ; preds = %while.body %5 = load i32* %i %add2 = add i32 %5, 1 store i32 %add2, i32* %i br label %if.end if.end: ; preds = %if.else, %if.then %6 = load i32* %loopCounter %add3 = add i32 %6, 1 store i32 %add3, i32* %loopCounter br label %while.cond after_ret: ; No predecessors! ret i32 0 } -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20150405/1d1ecfd2/attachment.html>
Mukul Sabharwal
2015-Apr-06 04:25 UTC
[LLVMdev] Unreachable br in IR but still seems to be executed
Your IR for the "if" doesn't seem to match what you've pasted, there are some additional load/stores which I don't see in your source. Maybe you're complaining about the "br label %if.end" (the one beyond the "br label %while.cond") A couple of ways to fix that: (1) Don't generate that extra br :-) (2) But maybe you want to faithfully represent the source code, which is a noble cause and in that case I suggest adding a "fake" basic block, perhaps call it "unreachable" and position the IRBuilder at that point, and if there are instructions from that point on they get stuffed in that unreachable BB. At this point you can ASSERT to your user, or maybe it's just a warning and you can simply apply the CFG Simplification Pass and call it a day. HTH, Mukul On Sun, Apr 5, 2015 at 8:54 PM, Dave Pitsbawn <dpitsbawn at gmail.com> wrote:> I'm trying to implement a continue statement like in C > > if (i % 2 == 0) > { > i = i + 1; > continue; > } > else > { > i = i + 1; > } > > My code generates IR like this, because of how I visit my AST, so when I > encounter a continue or break statement I go and find the corresponding > while. > > I was hoping LLVM would do the right thing which is ignore the unreachable > IR (br label %if.end). But it seems to somehow get to execute statements > after my br > > I've marked it with "SHOULD NOT HAPPEN" > define i32 @Main() { > entry: > %i = alloca i32 > %loopCounter = alloca i32 > store i32 0, i32* %i > store i32 0, i32* %loopCounter > br label %while.cond > while.cond: ; preds = %if.end, > %if.then, % > entry > %0 = load i32* %i > %cmptmp = icmp slt i32 %0, 100 > br i1 %cmptmp, label %while.body, label %while.end > while.body: ; preds = %while.cond > %1 = load i32* %i > %modtmp = srem i32 %1, 2 > %cmptmp1 = icmp eq i32 %modtmp, 0 > br i1 %cmptmp1, label %if.then, label %if.else > while.end: ; preds = %while.cond > %2 = load i32* %loopCounter > ret i32 %2 > if.then: ; preds = %while.body > %3 = load i32* %i > %add = add i32 %3, 1 > store i32 %add, i32* %i > br label %while.cond > %4 = load i32* %I <----------- SHOULD NOT HAPPEN > %sub = sub i32 %4, 1 > store i32 %sub, i32* %i > br label %if.end > if.else: ; preds = %while.body > %5 = load i32* %i > %add2 = add i32 %5, 1 > store i32 %add2, i32* %i > br label %if.end > if.end: ; preds = %if.else, > %if.then > %6 = load i32* %loopCounter > %add3 = add i32 %6, 1 > store i32 %add3, i32* %loopCounter > br label %while.cond > after_ret: ; No predecessors! > ret i32 0 > } > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev > >-------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20150405/bfaef789/attachment.html>
Kuperstein, Michael M
2015-Apr-06 07:27 UTC
[LLVMdev] Unreachable br in IR but still seems to be executed
Hello Dave, The problem is that this is not well-formed IR. A branch instruction is a terminator, and may only appear in the end of a basic block, never in the middle. You’ll need to split that basic block into two. Michael From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Dave Pitsbawn Sent: Monday, April 06, 2015 06:54 To: LLVM Developers Mailing List Subject: [LLVMdev] Unreachable br in IR but still seems to be executed I'm trying to implement a continue statement like in C if (i % 2 == 0) { i = i + 1; continue; } else { i = i + 1; } My code generates IR like this, because of how I visit my AST, so when I encounter a continue or break statement I go and find the corresponding while. I was hoping LLVM would do the right thing which is ignore the unreachable IR (br label %if.end). But it seems to somehow get to execute statements after my br I've marked it with "SHOULD NOT HAPPEN" define i32 @Main() { entry: %i = alloca i32 %loopCounter = alloca i32 store i32 0, i32* %i store i32 0, i32* %loopCounter br label %while.cond while.cond: ; preds = %if.end, %if.then, % entry %0 = load i32* %i %cmptmp = icmp slt i32 %0, 100 br i1 %cmptmp, label %while.body, label %while.end while.body: ; preds = %while.cond %1 = load i32* %i %modtmp = srem i32 %1, 2 %cmptmp1 = icmp eq i32 %modtmp, 0 br i1 %cmptmp1, label %if.then, label %if.else while.end: ; preds = %while.cond %2 = load i32* %loopCounter ret i32 %2 if.then: ; preds = %while.body %3 = load i32* %i %add = add i32 %3, 1 store i32 %add, i32* %i br label %while.cond %4 = load i32* %I <----------- SHOULD NOT HAPPEN %sub = sub i32 %4, 1 store i32 %sub, i32* %i br label %if.end if.else: ; preds = %while.body %5 = load i32* %i %add2 = add i32 %5, 1 store i32 %add2, i32* %i br label %if.end if.end: ; preds = %if.else, %if.then %6 = load i32* %loopCounter %add3 = add i32 %6, 1 store i32 %add3, i32* %loopCounter br label %while.cond after_ret: ; No predecessors! ret i32 0 } --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20150406/e00b68cb/attachment.html>