Sergey Dmitrouk
2014-Nov-07 09:54 UTC
[LLVMdev] Custom constraints in instruction schedulers
Hello Andrew, Dave, during review of http://reviews.llvm.org/D6054 it was suggested that I ask you of a better approach using instruction scheduler. What I'm trying to do --------------------- Ensuring that ldp-stp instruction pair used to implement inlined memcpy() have no instructions between them. Approaches that didn't work --------------------------- In general: * gluing * using TokenFactor node per load/store pair * pseudo-instruction (couldn't implement due to the need of temporary registers) In fact there were a lot of different modifications and mixes, none of which worked as expected. What works ---------- Manual reordering after all instruction scheduler passes. How scheduler could help ------------------------ I guess checking for registers and offset is enough to check for this special case, then scheduler could assume latency of load pair instruction to be zero in this particular case. I couldn't find a way to configure instruction scheduler in such a way. My questions is: is it actually possible or easy to add? Scheduler implementation doesn't seem to provide hooks to make such exceptions. Best regards, Sergey
Pierre-Andre Saulais
2014-Nov-07 10:40 UTC
[LLVMdev] Custom constraints in instruction schedulers
Hi Sergey, On 07/11/14 09:54, Sergey Dmitrouk wrote:> Hello Andrew, Dave, > > during review of http://reviews.llvm.org/D6054 it was suggested that I > ask you of a better approach using instruction scheduler. > > What I'm trying to do > --------------------- > > Ensuring that ldp-stp instruction pair used to implement inlined memcpy() > have no instructions between them. > > Approaches that didn't work > --------------------------- > > In general: > > * gluing > * using TokenFactor node per load/store pair > * pseudo-instruction (couldn't implement due to the need of temporary > registers)I haven't followed the review, so that I don't know whether this would work for you or not. Did you consider adding a 'def' operand to your pseudo-instruction? That should allow you to allocate a register for your temporary value. Of course, this only works if the pseudo instruction is created before register allocation.> > In fact there were a lot of different modifications and mixes, none of > which worked as expected. > > What works > ---------- > > Manual reordering after all instruction scheduler passes. > > How scheduler could help > ------------------------ > > I guess checking for registers and offset is enough to check for this > special case, then scheduler could assume latency of load pair instruction > to be zero in this particular case. > > I couldn't find a way to configure instruction scheduler in such a way. > My questions is: is it actually possible or easy to add? Scheduler > implementation doesn't seem to provide hooks to make such exceptions. > > Best regards, > Sergey > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev-- Pierre-Andre Saulais Compiler Developer Codeplay Software Ltd 45 York Place, Edinburgh, EH1 3HP Tel: 0131 466 0503 Fax: 0131 557 6600 Website: http://www.codeplay.com Twitter: https://twitter.com/codeplaysoft This email and any attachments may contain confidential and /or privileged information and is for use by the addressee only. If you are not the intended recipient, please notify Codeplay Software Ltd immediately and delete the message from your computer. You may not copy or forward it,or use or disclose its contents to any other person. Any views or other information in this message which do not relate to our business are not authorized by Codeplay software Ltd, nor does this message form part of any contract unless so stated. As internet communications are capable of data corruption Codeplay Software Ltd does not accept any responsibility for any changes made to this message after it was sent. Please note that Codeplay Software Ltd does not accept any liability or responsibility for viruses and it is your responsibility to scan any attachments. Company registered in England and Wales, number: 04567874 Registered office: 81 Linkfield Street, Redhill RH1 6BY
On 11/07/2014 04:54 AM, Sergey Dmitrouk wrote:> What I'm trying to do > --------------------- > > Ensuring that ldp-stp instruction pair used to implement inlined memcpy() > have no instructions between them.Hey Sergey, I only learned of clustering a short time ago, but it sounds like what you're after. The MIScheduler uses clusters as one of the heuristics. The idea is to ensure that instructions remain clustered (if possible) after scheduling to ensure later peephole optimizations still work. I haven't used it, so I can't speak to the effectiveness. Hope this helps. -Dave -- Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project