Hi Linhai,
See http://llvm.org/docs/WritingAnLLVMBackend.html#id14 for a description
of how an LLVM backend describes machine instructions. LLVM has its own
declarative language for this, called TableGen.
However, the semantics description is limited: you specify instruction
behaviour in the form of LLVM IR DAGs that matches the functionality
provided by an instruction. As you may have guessed, this will be used by
the instruction selection algorithm. It is limited because some
instructions may lack such information, requiring custom C++ code to select
them.
An easy way to dump all information TableGen has about an architecture
(X86, for instance) is to use the llvm-tblgen tool. If you built LLVM
yourself, you will have it, but I am not sure if pre-built packages include
it. Run it like this:
$ cd <myllvmsrc>/lib/Target/X86 # X86 backend folder
$ llvm-tblgen -print-records X86.td -I=../../../include &>
<myfile.txt>
Now open <myfile.txt>, a huge dump with all TableGen records for this
architecture. Search for "-- Defs --", this string marks where all
record
definitions begin. You will see struct-like entities with all the
information TableGen knows about each X86 instruction. What you are looking
for is the "Pattern" field, a DAG describing this instruction
semantics in
terms of the LLVM IR.
Hope this helps,
Rafael
On Fri, Aug 22, 2014 at 12:54 AM, Linhai <songlh at cs.wisc.edu> wrote:
> Hi,
>
> I am wondering whether LLVM code generators have a table describing
> the x86-64 instructions semantics, something like a register transfer
> language for all x86-64 instructions?
>
> Thanks a lot!
>
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