llvm dev - Aug 2014 - [LLVMdev] [AMDGPU][PATCH 3/3] Stubs implementation of the new intrinsics on Southern_Islands

This patch is a first implementation of the newly added
intrinsics for barriers/memory fences on SI. For ultra-simplicity, every
intrinsic is lowered to a barrier with no fence.

Signed-off-by: Damien Hilloulin <damien.hilloulin at supelec.fr>
---
  lib/Target/R600/SIInstructions.td | 16 +++++++++++++++-
  1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/lib/Target/R600/SIInstructions.td 
b/lib/Target/R600/SIInstructions.td
index fd011a1..31f4e77 100644
--- a/lib/Target/R600/SIInstructions.td
+++ b/lib/Target/R600/SIInstructions.td
@@ -426,7 +426,21 @@ def S_CBRANCH_EXECNZ : SOPP <

  let hasSideEffects = 1 in {
  def S_BARRIER : SOPP <0x0000000a, (ins), "S_BARRIER",
-  [(int_AMDGPU_barrier_local)]
+  [
+    (int_AMDGPU_barrier_nofence),//only correct pattern
+    (int_AMDGPU_barrier_local),//those patterns are stubs
+    (int_AMDGPU_barrier_global),
+    (int_AMDGPU_barrier_localglobal),
+    (int_AMDGPU_mem_fence_local),//those patterns are stubs
+    (int_AMDGPU_mem_fence_global),
+    (int_AMDGPU_mem_fence_localglobal),
+    (int_AMDGPU_read_mem_fence_local),//those patterns are stubs
+    (int_AMDGPU_read_mem_fence_global),
+    (int_AMDGPU_read_mem_fence_localglobal),
+    (int_AMDGPU_write_mem_fence_local),//those patterns are stubs
+    (int_AMDGPU_write_mem_fence_global),
+    (int_AMDGPU_write_mem_fence_localglobal)
+  ]
  > {
    let simm16 = 0;
    let isBarrier = 1;
-- 
1.9.1