llvm dev - Aug 2014 - [LLVMdev] Concerning not relevant argument count in TableGen Patterns.

Dear all.

I have a problem with the following situation:

I want to handle an intrinsic function in a specific way. The prototype of
my function is:    "/int my_intrinsic_name()/"

So I want to generate a move instruction which should use two register type
operands:   "/mov R1, R2/"

For this purpose I assume that the instruction definition in the
TargetInstrInfo.td file should be like:

at first I am defining the class form my instruction:
*class Mymov<bits&lt;6> op, string instr_asm>:  FI<op, (outs
Regs1:$rs),
(ins Regs2:$rt),
     !strconcat(instr_asm, &quot;\t$rt, $rs&quot;), 
     [], NoItinerary> {
     let imm16 = 0;
}*

where *Regs1* and *Regs2* are corresponding *RegisterClasses*. 
Then I need to define the instruction:
*def MOVInstr : Mymov<0x2, "mov">;*
*def : TargetPat<(int_myintrinsicname), (MOVInstr)>;*   /// error: In
anonymous.4: Instruction 'MOVInstr' expects more operands than were
provided./

int the corresponding /inclue/llvm/IR/IntrinsicsTarget.td/ file:

*def int_myintrinsicname : Intrinsic< [llvm_i16_ty], [],
[<IntrinsicProperty>], "llvm.my_intrinsic_name" >;*

This causes an error (shown in a comment) because I have specified an
instruction class which has two operands (one in "outs" list and the
other
one in "ins" list, but pattern knows that the SRC has one operand
(return
type of the int_myintrinsicname) if i am not mistaken.


So, is there a technique to handle this kind of situation using Tablegen?
Can I use a Pattern when the argument count of SRC and DST does not match to
each other ?

Thanks,
Arsen



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On Tue, Aug 05, 2014 at 01:50:26AM -0700, Arsen Hakobyan
wrote:
> Dear all.
> 
> I have a problem with the following situation:
> 
> I want to handle an intrinsic function in a specific way. The prototype of
> my function is:    "/int my_intrinsic_name()/"
> 
> So I want to generate a move instruction which should use two register type
> operands:   "/mov R1, R2/"
> 
> For this purpose I assume that the instruction definition in the
> TargetInstrInfo.td file should be like:
> 
> at first I am defining the class form my instruction:
> *class Mymov<bits&lt;6> op, string instr_asm>:  FI<op,
(outs Regs1:$rs),
> (ins Regs2:$rt),
>      !strconcat(instr_asm, &quot;\t$rt, $rs&quot;), 
>      [], NoItinerary> {
>      let imm16 = 0;
> }*
> 
> where *Regs1* and *Regs2* are corresponding *RegisterClasses*. 
> Then I need to define the instruction:
> *def MOVInstr : Mymov<0x2, "mov">;*
> *def : TargetPat<(int_myintrinsicname), (MOVInstr)>;*   /// error: In
> anonymous.4: Instruction 'MOVInstr' expects more operands than were
> provided./
> 
> int the corresponding /inclue/llvm/IR/IntrinsicsTarget.td/ file:
> 
> *def int_myintrinsicname : Intrinsic< [llvm_i16_ty], [],
> [<IntrinsicProperty>], "llvm.my_intrinsic_name" >;*
> 
> This causes an error (shown in a comment) because I have specified an
> instruction class which has two operands (one in "outs" list and
the other
> one in "ins" list, but pattern knows that the SRC has one operand
(return
> type of the int_myintrinsicname) if i am not mistaken.
> 
> 
> So, is there a technique to handle this kind of situation using Tablegen?
> Can I use a Pattern when the argument count of SRC and DST does not match
to
> each other ?
>
If I understand correctly, you are trying to match an intrinsic with one
output and no inputs to an instruction with one output and one input.

It may help if you could give a little more detail about what the intrinsic
is supposed to do.  Does it return a value from a status register?

To get you pattern to work, you will have to do something like:

def : TargetPat <
  (int_myintrinsicname),
  (MOVInstr STATUS_REG)
>;
Where STATUS_REG is one of the registers defined in your *RegisterInfo.td
file.

-Tom
> Thanks,
> Arsen
> 
> 
> 
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Hi Tom.

Thank you very much! Actually, yes, I am trying to use some status register.
And the definition you have suggested is what I need. 

- Arsen



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