Ghassan Shobaki
2013-Sep-26 07:30 UTC
[LLVMdev] Enabling MI Scheduler on x86 (was Experimental Evaluation of the Schedulers in LLVM 3.3)
So, when the MI scheduler is enabled, will SD scheduling be totally disabled or the SD scheduler will be automatically set to do source scheduling? -Ghassan ________________________________ From: Andrew Trick <atrick at apple.com> To: llvmdev at cs.uiuc.edu Cc: Ghassan Shobaki <ghassan_shobaki at yahoo.com> Sent: Thursday, September 26, 2013 9:24 AM Subject: Re: [LLVMdev] Enabling MI Scheduler on x86 (was Experimental Evaluation of the Schedulers in LLVM 3.3) On Sep 23, 2013, at 11:36 PM, Chandler Carruth <chandlerc at google.com> wrote:> >On Tue, Sep 24, 2013 at 1:11 AM, Andrew Trick <atrick at apple.com> wrote: > >This week, I'll see if we can enable MI scheduling by default for x86. I'm not sure which flags you're using to test it now. But by making it default and enabling the corresponding coalescer changes, we can be confident that benchmarking efforts are improving on the same baseline. >While I'm generally really excited by this, I would ask for a bit more staging of this change. > > >Specifically, I would really like for a single, clear switch to enable exactly what you want benchmark data on *before* it becomes the default, and to give various folks time to run benchmarks and report serious regressions. > > >I don't want our ability to ship LLVM from top-of-tree to be seriously impaired by this, and enabling a feature that can have dramatic performance impact without a giving folks a really simple way to try it out and a period of time to run benchmarks and collect data seems to do that. =/ > > >Once it is the default, it would be really good to leave in the single, simple switch for a period of time for folks to disable it if need be.I just added a flag: -misched-bench. You can use it to flip back and forth between your target's default SD scheduler and the machine scheduler. It's doesn't affect whether the postRA scheduler is also run. -Andy -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130926/4337b142/attachment.html>
Tim Northover
2013-Sep-26 07:41 UTC
[LLVMdev] Enabling MI Scheduler on x86 (was Experimental Evaluation of the Schedulers in LLVM 3.3)
On 26 September 2013 08:30, Ghassan Shobaki <ghassan_shobaki at yahoo.com> wrote:> So, when the MI scheduler is enabled, will SD scheduling be totally disabled > or the SD scheduler will be automatically set to do source scheduling?The latter. The SD scheduler is where the DAG is converted into the linear MachineInstr representation. Some kind of scheduling *has* to happen. Tim.
Andrew Trick
2013-Sep-26 15:41 UTC
[LLVMdev] Enabling MI Scheduler on x86 (was Experimental Evaluation of the Schedulers in LLVM 3.3)
On Sep 26, 2013, at 12:41 AM, Tim Northover <t.p.northover at gmail.com> wrote:> On 26 September 2013 08:30, Ghassan Shobaki <ghassan_shobaki at yahoo.com> wrote: >> So, when the MI scheduler is enabled, will SD scheduling be totally disabled >> or the SD scheduler will be automatically set to do source scheduling?It’s set to source scheduling to emulate what will happen when it’s disabled.> The latter. The SD scheduler is where the DAG is converted into the > linear MachineInstr representation. Some kind of scheduling *has* to > happen.Right. We want to replace the expensive SD scheduler, which builds yet another SUnit DAG on top of the SD DAG with a routine that orders the SD nodes and breaks physical register interference. -Andy
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