Hello LLVMdev,
Our processor has mac (multiply and accumulate) instructions which takes
the accumulator register (acc) as an implicit operand. This is different
from typical three or four operands mac instructions. As an illustration,
the following instructions compute a + b x c + e x f + g *h.
initacc a //initialize the accumulator register
fmac b c
fmac e f
fmac g h
mfacc i //move result from the accumulator
register to register i
A straightforward implementation is to find the patterns in selectionDAG
and turn them into mac instructions chains like above. One chain of mac
instructions (with initacc at the beginning and mfacc at the end) may be
glued together to be one unit, so that the scheduler would not interleave
instructions from different chains.
However this implementation is not efficient.
1. The scheduler cannot insert instructions between mac instructions to
fill pipeline bubble, since one chain is one schedule unit.
2. Register pressure will be high if the mac chains are long, since all
the input registers of one chain are alive at the same time.
I try to solve the problem by not just glue one chain of mac instructions
together, instead by using virtual data dependency
and implicit physical register dependency. I do get good results. However
my implementation needs to modify target-independent llvm scheduler code,
so it is not flexible and error-prone.
I would much appreciate if you could give some suggestions or bring some
ideas. Thanks!
Best regards,
David
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