llvm dev - Jan 2012 - [LLVMdev] Tablegen: How to define an instruction that reads and writes the same register

Hi,

Is it possible to define an Instruction with tablegen that reads and
writes the same register?  For example, an increment instruction that
reads a value from a register, adds one to it and then writes the result
back to the same register.

Thanks,
Tom

On Thu, Jan 19, 2012 at 6:07 PM, Tom Stellard <thomas.stellard at amd.com>
wrote:
> Hi,
>
> Is it possible to define an Instruction with tablegen that reads and
> writes the same register?  For example, an increment instruction that
> reads a value from a register, adds one to it and then writes the result
> back to the same register.
Yes; you just write the instruction as if the dest and src are
distinct, then specify 'let Constraints = "$src1 = $dst"'. 
See for
example INC32r in the x86 backend.

-Eli

Hi Tom

This is frequently done in the x86 target using a tablegen constraint.

For example, from X86InstrArithmetic.td we have

let Constraints = "$src1 = $dst" in {
def INC8r  : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
               "inc{b}\t$dst",
               [(set GR8:$dst, EFLAGS, (X86inc_flag GR8:$src1))]>;
}

Thanks,
Pete

On Jan 19, 2012, at 6:07 PM, Tom Stellard wrote:
> Hi,
> 
> Is it possible to define an Instruction with tablegen that reads and
> writes the same register?  For example, an increment instruction that
> reads a value from a register, adds one to it and then writes the result
> back to the same register.
> 
> Thanks,
> Tom
> 
> 
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