llvm dev - Dec 2011 - [LLVMdev] Vector immediates in tablegen w/o build_vector?

I have two patterns in tablegen that do look like the exact same thing:
Pat 1)
  def MOV_v4i16 : ILFormat<IL_OP_MOV, (outs GPRV4I16:$dst),
      (ins i16imm:$val),
      asm, [(set GPRV4I16:$dst, (build_vector (i16 imm:$val)))]>;
Pat 2)
def v4i16imm : Operand<v4i16>;
  def MOV_v4i16 : ILFormat<IL_OP_MOV, (outs GPRV4I16:$dst),
      (ins v4i16imm:$val),
      asm, [(set GPRV4I16:$dst, (v4i16 imm:$val))]>;

The second pattern seems to build correctly, but doesn't match because of
the build_vector opcode.

So, what I am trying to figure out, how do I get (build_vector (i16 imm:$val))
to be convert to v4i16 immediate directly?

I've tried pattern fragments, but I can't seem to get that to work
correctly.

I tried this:
def v4i16imm : Operand<v4i16>;
def bvimm : PatFrag<(ops node:$val), (build_vector node:$val)>;
def _v4i16 : ILFormat<IL_OP_MOV, (outs GPRV4I16:$dst),
      (ins v4i16imm:$val),
      asm, [(set GPRV4I16:$dst, (v4i16 (bvimm imm:$val)))]>;

Any idea? Basically I am trying to get vector immediates to work in tablegen
patterns.

Thanks,
Micah
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Here is my test case I am trying to match in as few instruction as possible,
currently it takes a dozen or so.
define void @__OpenCL_bug7669_kernel(<4 x i16> addrspace(1)* nocapture %a)
nounwind {
entry:
  store <4 x i16> <i16 0, i16 1, i16 2, i16 3>, <4 x i16>
addrspace(1)* %a, align 8
  ret void
}

From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On
Behalf Of Villmow, Micah
Sent: Thursday, December 15, 2011 4:04 PM
To: LLVM Developers Mailing List
Subject: [LLVMdev] Vector immediates in tablegen w/o build_vector?

I have two patterns in tablegen that do look like the exact same thing:
Pat 1)
  def MOV_v4i16 : ILFormat<IL_OP_MOV, (outs GPRV4I16:$dst),
      (ins i16imm:$val),
      asm, [(set GPRV4I16:$dst, (build_vector (i16 imm:$val)))]>;
Pat 2)
def v4i16imm : Operand<v4i16>;
  def MOV_v4i16 : ILFormat<IL_OP_MOV, (outs GPRV4I16:$dst),
      (ins v4i16imm:$val),
      asm, [(set GPRV4I16:$dst, (v4i16 imm:$val))]>;

The second pattern seems to build correctly, but doesn't match because of
the build_vector opcode.

So, what I am trying to figure out, how do I get (build_vector (i16 imm:$val))
to be convert to v4i16 immediate directly?

I've tried pattern fragments, but I can't seem to get that to work
correctly.

I tried this:
def v4i16imm : Operand<v4i16>;
def bvimm : PatFrag<(ops node:$val), (build_vector node:$val)>;
def _v4i16 : ILFormat<IL_OP_MOV, (outs GPRV4I16:$dst),
      (ins v4i16imm:$val),
      asm, [(set GPRV4I16:$dst, (v4i16 (bvimm imm:$val)))]>;

Any idea? Basically I am trying to get vector immediates to work in tablegen
patterns.

Thanks,
Micah
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Micah,

This is related to a question that I asked back in October about
matching addsub instructions. Duncan had a suggestion, see:
http://lists.cs.uiuc.edu/pipermail/llvmdev/2011-October/044322.html

Unfortunately, as it stands, you currently cannot match build_vector
like this. IIRC, it is always turned into constant loads before nodes
are matched (see also the aforementioned thread). In my opinion, it
would be reasonable to change this.

 -Hal

On Fri, 2011-12-16 at 00:03 +0000, Villmow, Micah wrote:
> I have two patterns in tablegen that do look like the exact same
> thing:
> 
> Pat 1)
> 
>   def MOV_v4i16 : ILFormat<IL_OP_MOV, (outs GPRV4I16:$dst),
> 
>       (ins i16imm:$val),
> 
>       asm, [(set GPRV4I16:$dst, (build_vector (i16 imm:$val)))]>;
> 
> Pat 2)
> 
> def v4i16imm : Operand<v4i16>;
> 
>   def MOV_v4i16 : ILFormat<IL_OP_MOV, (outs GPRV4I16:$dst),
> 
>       (ins v4i16imm:$val),
> 
>       asm, [(set GPRV4I16:$dst, (v4i16 imm:$val))]>;
> 
>  
> 
> The second pattern seems to build correctly, but doesn't match because
> of the build_vector opcode.
> 
>  
> 
> So, what I am trying to figure out, how do I get (build_vector (i16
> imm:$val)) to be convert to v4i16 immediate directly?
> 
>  
> 
> I've tried pattern fragments, but I can't seem to get that to work
> correctly.
> 
>  
> 
> I tried this:
> 
> def v4i16imm : Operand<v4i16>;
> 
> def bvimm : PatFrag<(ops node:$val), (build_vector node:$val)>;
> 
> def _v4i16 : ILFormat<IL_OP_MOV, (outs GPRV4I16:$dst),
> 
>       (ins v4i16imm:$val),
> 
>       asm, [(set GPRV4I16:$dst, (v4i16 (bvimm imm:$val)))]>;
> 
>  
> 
> Any idea? Basically I am trying to get vector immediates to work in
> tablegen patterns.
> 
>  
> 
> Thanks,
> 
> Micah
> 
> 
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
-- 
Hal Finkel
Postdoctoral Appointee
Leadership Computing Facility
Argonne National Laboratory