llvm dev - Nov 2011 - [LLVMdev] x86 backend assembly - mov esp->reg

Hi,

I've noticed an inconsistency with the x86 backend assembly output in how it
treats arguments of a function. Here is a simple test to illustrate the
inconsistency:

<from test.c>
void test()
{
  char ac, bc, cc, dc, fc;

  ac = (char)Rand();
  bc = (char)Rand();
  cc = (char)Rand();
  dc = (char)Rand();

  fc = PartialRegisterOperationsTestChar(ac, bc, cc, dc);
}

<from partialregisteroperations.c>
char PartialRegisterOperationsTestChar(char a, char b, char c, char d)
{
  return a*b+c*d;
}

When compiled for atom with clang in 32-bit mode the 8-bit variables in test use
32-bit registers:
       ...
       movl   %ecx, 8(%esp)
       ...
       movl   %ecx, 4(%esp)
       ...
       movl   %ecx, (%esp)
       ...
       movl   %eax, 12(%esp)
       calll  _PartialRegisterOperationsTestChar

However, the 8-bit variables in PartialRegisterOperationsTestChar use 8-bit
registers:

_PartialRegisterOperationsTestChar:     # @PartialRegisterOperationsTestChar
# BB#0:                                 # %entry
       movb   16(%esp), %dl
       movb   8(%esp), %al
       mulb   4(%esp)
       movb   %al, %cl
       movb   %dl, %al
       mulb   12(%esp)
       addb   %cl, %al
       movsbl %al, %eax
       ret

I am interested in learning how to change the 8-bit variables in
PartialRegisterOperationsTestChar to use 32-bit registers. However, I am new to
LLVM and not sure how to do this. I've been trying to find where the mov
esp->reg instructions are generated but I haven't had much luck. Could
anyone point me in the right direction? Or suggest an another approach for
solving this problem?

Comments and suggestions are appreciated,

Tyler Nowicki
Software Developer
Intel Corporation
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On Thu, Nov 24, 2011 at 11:39:32AM -0700, Nowicki, Tyler
wrote:
> When compiled for atom with clang in 32-bit mode the 8-bit variables
> in test use 32-bit registers:
That's fine since it can avoid partial stales and the value of the
padding is undefined.
> However, the 8-bit variables in PartialRegisterOperationsTestChar use
> 8-bit registers:
Same argument. It wants to use the value of the 8bit registers, so
setting them up via 32bit ops could create a partial register stale.

Do you disagree?

Joerg

I'm not an expert in this area, I'm just going off of the Intel 64 and
IA-32 Architectures Optimization Reference Manual. Also, I'm looking at atom
on llvm which has its own set of limitations. From page 595, section 13.3.3.5
Parameter Passing, 'For Intel Atom processors, "bool" and
"char" value should be passed onto and read off of the stack as 32-bit
data.' The description is a little longer if you want to read more.

http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-optimization-manual.html

Tyler Nowicki
Software Developer
Intel Corporation

-----Original Message-----
From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On
Behalf Of Joerg Sonnenberger
Sent: Thursday, November 24, 2011 14:02 PM
To: llvmdev at cs.uiuc.edu
Subject: Re: [LLVMdev] x86 backend assembly - mov esp->reg

On Thu, Nov 24, 2011 at 11:39:32AM -0700, Nowicki, Tyler
wrote:
> When compiled for atom with clang in 32-bit mode the 8-bit variables 
> in test use 32-bit registers:
That's fine since it can avoid partial stales and the value of the padding
is undefined.
> However, the 8-bit variables in PartialRegisterOperationsTestChar use 
> 8-bit registers:
Same argument. It wants to use the value of the 8bit registers, so setting them
up via 32bit ops could create a partial register stale.

Do you disagree?

Joerg
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