Tom Stellard
2011-Nov-03 17:22 UTC
[LLVMdev] Tablegen: Instructions that take immediates or registers as operands
Hi, I'm working on an LLVM backend for GPUs. One thing that is a little different about some GPUs is that instructions can take registers or 32-bit floating point immediates as arguments. I was wondering if there is a way to model this using tablegen, without having to define an instruction for each possible combination of registers and immediates (e.g. For ADD it would require four definitions: ADD_imm_imm, ADD_reg_reg, ADD_imm_reg, ADD_reg_imm). I have tried a few different ways to make this work in tablegen, but I have been unsuccessful so far. Here is an example of something I have tried. It fails to compile with tablegen, but I hope it can help demonstrate what I am trying to do: def F32Node : PatLeaf<(vt), [{return N->getVT() == MVT::f32;}]>; def F32Op : Operand <f32> { let MIOperandInfo = (ops GPR, f32imm); } def ADD : InstAMD < (outs GPR:$dst), (ins F32Op:$src0, F32Op:$src1), "ADD $dst, $src0, $src1"), [(set GPR:$dst, (fadd F32Node:$src0, F32Node:$src1))] >; Is what I am trying to do possible with tablegen, and if so what is the best way for me to do it? Thanks, Tom Stellard
Villmow, Micah
2011-Nov-03 18:40 UTC
[LLVMdev] Tablegen: Instructions that take immediates or registers as operands
Tom, There is no way to do this that I know of. Maybe David Greene or someone who hacks on Tablegen a lot would know. Micah> -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] > On Behalf Of Tom Stellard > Sent: Thursday, November 03, 2011 10:23 AM > To: LLVM Developers Mailing List > Subject: [LLVMdev] Tablegen: Instructions that take immediates or > registers as operands > > Hi, > > I'm working on an LLVM backend for GPUs. One thing that is a little > different about some GPUs is that instructions can take registers or > 32-bit floating point immediates as arguments. I was wondering if > there > is a way to model this using tablegen, without having to define an > instruction for each possible combination of registers and immediates > (e.g. For ADD it would require four definitions: ADD_imm_imm, > ADD_reg_reg, ADD_imm_reg, ADD_reg_imm). > > I have tried a few different ways to make this work in tablegen, but I > have been unsuccessful so far. Here is an example of something I have > tried. It fails to compile with tablegen, but I hope it can help > demonstrate what I am trying to do: > > > def F32Node : PatLeaf<(vt), [{return N->getVT() == MVT::f32;}]>; > > def F32Op : Operand <f32> { > let MIOperandInfo = (ops GPR, f32imm); > } > > def ADD : InstAMD < > (outs GPR:$dst), > (ins F32Op:$src0, F32Op:$src1), > "ADD $dst, $src0, $src1"), > [(set GPR:$dst, (fadd F32Node:$src0, F32Node:$src1))] > >; > > Is what I am trying to do possible with tablegen, and if so what is the > best way for me to do it? > > Thanks, > Tom Stellard > > > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
Justin Holewinski
2011-Nov-03 19:14 UTC
[LLVMdev] Tablegen: Instructions that take immediates or registers as operands
On Thu, Nov 3, 2011 at 2:40 PM, Villmow, Micah <Micah.Villmow at amd.com>wrote:> Tom, > There is no way to do this that I know of. Maybe David Greene or someone > who hacks on Tablegen a lot would know. >This particular problem is not so bad with the use of multiclass and mdef. It at least lets you factor out the redundancy across different instructions.> > Micah > > > -----Original Message----- > > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] > > On Behalf Of Tom Stellard > > Sent: Thursday, November 03, 2011 10:23 AM > > To: LLVM Developers Mailing List > > Subject: [LLVMdev] Tablegen: Instructions that take immediates or > > registers as operands > > > > Hi, > > > > I'm working on an LLVM backend for GPUs. One thing that is a little > > different about some GPUs is that instructions can take registers or > > 32-bit floating point immediates as arguments. I was wondering if > > there > > is a way to model this using tablegen, without having to define an > > instruction for each possible combination of registers and immediates > > (e.g. For ADD it would require four definitions: ADD_imm_imm, > > ADD_reg_reg, ADD_imm_reg, ADD_reg_imm). > > > > I have tried a few different ways to make this work in tablegen, but I > > have been unsuccessful so far. Here is an example of something I have > > tried. It fails to compile with tablegen, but I hope it can help > > demonstrate what I am trying to do: > > > > > > def F32Node : PatLeaf<(vt), [{return N->getVT() == MVT::f32;}]>; > > > > def F32Op : Operand <f32> { > > let MIOperandInfo = (ops GPR, f32imm); > > } > > > > def ADD : InstAMD < > > (outs GPR:$dst), > > (ins F32Op:$src0, F32Op:$src1), > > "ADD $dst, $src0, $src1"), > > [(set GPR:$dst, (fadd F32Node:$src0, F32Node:$src1))] > > >; > > > > Is what I am trying to do possible with tablegen, and if so what is the > > best way for me to do it? > > > > Thanks, > > Tom Stellard > > > > > > > > _______________________________________________ > > LLVM Developers mailing list > > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev > > > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev >-- Thanks, Justin Holewinski -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20111103/a74cc980/attachment.html>
David A. Greene
2011-Nov-07 19:18 UTC
[LLVMdev] Tablegen: Instructions that take immediates or registers as operands
"Villmow, Micah" <Micah.Villmow at amd.com> writes:> Tom,> There is no way to do this that I know of. Maybe David Greene or > someone who hacks on Tablegen a lot would know.There's no way currently without major TableGen hacking. -Dave