maarten faddegon
2010-Nov-25 13:02 UTC
[LLVMdev] ARM Intruction Constraint DestReg!=SrcReg patch?
Hi, I am using a cross compiler to compiler for the arm5 architecture. For this architecture it is not allowed that a destination register is also used as source register. In 2007 a patch was discussed at the mailing list, however my compiler still is producing this result. Does anyone know if this patch is actually applied? * I use the following arguments: llvm-gcc -mfpu=vfp -mlittle-endian -mfloat-abi=softfp -march=armv5 -S -O3 foo.c -S -o foo.s * Attached to this document foo.c and the resulting foo.s. Please, take note of the illegal instruction mul r0, r0, r2 at line 18. * The patch is discussed at: http://www.mail-archive.com/llvm-commits at cs.uiuc.edu/msg14069.html * llvm-gcc --version llvm-gcc (GCC) 4.2.1 (Based on Apple Inc. build 5658) (LLVM build) Copyright (C) 2007 Free Software Foundation, Inc. kind regards, Maarten Faddegon -------------- next part -------------- A non-text attachment was scrubbed... Name: foo.c Type: text/x-csrc Size: 77 bytes Desc: not available URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20101125/e8eef35b/attachment.c> -------------- next part -------------- .syntax unified .cpu arm10tdmi .eabi_attribute 10, 2 .eabi_attribute 20, 1 .eabi_attribute 21, 1 .eabi_attribute 23, 3 .eabi_attribute 24, 1 .eabi_attribute 25, 1 .file "foo.c" .text .globl foo .align 2 .type foo,%function foo: ldr r1, .LCPI0_0 ldr r0, [r1] mov r2, #123 mul r0, r0, r2 mov r2, #15 orr r2, r2, #15, 24 add r0, r0, #114, 30 and r0, r0, r2 str r0, [r1] bx lr .align 2 .LCPI0_0: .long bar .Ltmp0: .size foo, .Ltmp0-foo .type bar,%object .comm bar,4,4 .ident "GCC: (GNU) 4.2.1 (Based on Apple Inc. build 5658) (LLVM build)"
Paul Curtis
2010-Nov-25 14:50 UTC
[LLVMdev] ARM Intruction Constraint DestReg!=SrcReg patch?
Hi,> I am using a cross compiler to compiler for the arm5 architecture. Forthis> architecture it is not allowed that a destination register is also used assource> register. > In 2007 a patch was discussed at the mailing list, however my compilerstill is> producing this result. Does anyone know if this patch is actually applied? > > * I use the following arguments: > llvm-gcc -mfpu=vfp -mlittle-endian -mfloat-abi=softfp -march=armv5 -S > -O3 foo.c -S -o foo.s > * Attached to this document foo.c and the resulting foo.s. Please, takenote of> the illegal instruction mul r0, r0, r2 at line 18. > * The patch is discussed at: > http://www.mail-archive.com/llvm-commits at cs.uiuc.edu/msg14069.html > * llvm-gcc --version > llvm-gcc (GCC) 4.2.1 (Based on Apple Inc. build 5658) (LLVM build)Copyright> (C) 2007 Free Software Foundation, Inc.If you read the Arm Architecture document for ARMv5, it states for MUL: "Operand restriction: Specifying the same register for <Rd> and <Rm> was previously described as producing UNPREDICTABLE results. There is no restriction in ARMv6, and it is believed all relevant ARMv4 and ARMv5 implementations do not require this restriction either, because high performance multipliers read all their operands prior to writing back any results." Therefore I do not believe you need to worry about this at all. -- Paul Curtis, Rowley Associates Ltd http://www.rowley.co.uk SolderCore arriving Winter 2010! http://www.soldercore.com
maarten faddegon
2010-Nov-26 07:59 UTC
[LLVMdev] ARM Intruction Constraint DestReg!=SrcReg patch?
Hi, Paul Curtis wrote:> If you read the Arm Architecture document for ARMv5, it states for MUL: > > "Operand restriction: Specifying the same register for <Rd> and <Rm> was > previously described as producing UNPREDICTABLE results. There is no > restriction in ARMv6, and it is believed all relevant ARMv4 and ARMv5 > implementations do not require this restriction either, because high > performance multipliers read all their operands prior to writing back any > results." > > Therefore I do not believe you need to worry about this at all.However, ARM support wrote:> The restriction on Rd == Rm was removed in ARMv6, but this was not a > retrospective change. That is, for ARMv4T and ARMv5TE the combination is > still officially unpredictable. > > The comment in the ARM Architecture Reference Manual is intended as a > helpful note. However, in some ways it is unhelpful as there is still > no guarentee that a given implementation will support it.The > comment has since been removed from the latest edition. > > The advise would be to assume that restriction still applies to ARMv4T or > ARMv5TE when developing portable codeThus, if I want to follow this advice, is there a way to force LLVM to not output instructions such as "mul r0, r0, r2"? As I believe was the effect of the Lauro Ramos Venancio's patch. kind regards, Maarten Faddegon
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