Anton Korobeynikov wrote:> Hello > "T2Divide" should be a subtarget feature bit. This way it can be > "automatically" assigned to the procesor.I agree this is a better approach.> The instruction selection patterns for t2{S,U}DIV should be also > guarded by this predicate.Is this necessary? Since the absence of the predicate causes lowering to expand divides, the pattern should never show up.> > Also, for cortex-m3 it will be nice to have separate V7M feature profile. >Agreed. Now how do we get this done? regards, bagel
Hello> Is this necessary? Since the absence of the predicate causes lowering to > expand divides, the pattern should never show up.Just to guard codegen bugs. If anything went wrong (when predicates will be used) then you'll get nice assertion "cannot yet select".> Agreed. Now how do we get this done?Just look how ArmV7A is defined and do something similar... -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University
Anton Korobeynikov wrote:> Hello > >> Is this necessary? Since the absence of the predicate causes lowering to >> expand divides, the pattern should never show up. > Just to guard codegen bugs. If anything went wrong (when predicates > will be used) then you'll get nice assertion "cannot yet select". > >> Agreed. Now how do we get this done? > Just look how ArmV7A is defined and do something similar... >It's not clear to me how to add the V7m architecture without breaking something. The predicates that use ARMArchEnum assume an ordering. And V7m is a subset of v7a (and of v6t2). So a strict ordering scheme starts to break down. I think I'll just enter this in the bug list and let people who understand the subtarget implications do the fix. regards, bagel