On Sun, 2008-10-19 at 23:18 -0700, Evan Cheng wrote:> > On Oct 18, 2008, at 7:01 AM, sanjiv gupta wrote: > > > On Thu, 2008-10-16 at 08:55 -0700, Evan Cheng wrote: > > > On Oct 15, 2008, at 11:21 AM, sanjiv gupta wrote: > > > > > > > > > > > > > > > > > > > Ok. The AX / AH super-reg and sub-reg relationship is not > > > > > defined. In > > > > > general x86 is not making good use of the high 8-bit > > > > > sub-registers. > > > > > We > > > > > are leaving some performance on the table. We'll probably fix > > > > > it one > > > > > day. However, this doesn't apply to your target, right? There > > > > > is > > > > > nothing preventing you from specifying the sub-registers and > > > > > making > > > > > use of insert_subreg, no? > > > > > > > > > > Evan > > > > > > > > > it is, though we have a workaround. > > > > > > > > We have 16-bit registers class and want to set both the lo and > > > > high > > > > parts using INSERT_SUBREG. > > > > > > > > The workaround is to declare the same SubRegClass twice while > > > > declaring > > > > the SuperRegisterClass. i.e. > > > > > > > > def FSR16: RegisterClass <"PIC16", [i16], 8, [FSR0, FSR1]> { > > > > let SubRegClassList = [FSR8, FSR8]; // HERE. > > > > } > > > > > > This is a bug, probably in tablegen. Unfortunately I don't have > > > the > > > time to fix it. But please file a bug about this. Hopefully > > > someone > > > will fix it soon. > > > > > > Thanks, > > > > > > Evan > > > > > > > PR2916 filed. > > Though I did not quite understand why this could be a tablegen bug? > > > Based on your comments. :-) It should be possible to specify two FSR0 > sub-registers (FSR0L, FSR0H of the same register class FSR8) with the > workaround you described: > > > def FSR16: RegisterClass <"PIC16", [i16], 8, [FSR0, FSR1]> { > let SubRegClassList = [FSR8, FSR8]; // HERE. > } >It is currently possible. - Sanjiv> > Evan > > > > > > > - Sanjiv > > > > > > _______________________________________________ > > LLVM Developers mailing list > > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev > > > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
On Oct 20, 2008, at 7:10 AM, sanjiv gupta wrote:>>> >>> PR2916 filed. >>> Though I did not quite understand why this could be a tablegen bug? >> >> >> Based on your comments. :-) It should be possible to specify two FSR0 >> sub-registers (FSR0L, FSR0H of the same register class FSR8) with the >> workaround you described: >> >> >> def FSR16: RegisterClass <"PIC16", [i16], 8, [FSR0, FSR1]> { >> let SubRegClassList = [FSR8, FSR8]; // HERE. >> } >> > It is currently possible.I am confused. Is what you described in PR2916 an issue or not? Evan> > > - Sanjiv > >> >> Evan >> >>> >>> >>> - Sanjiv >>> >>> >>> _______________________________________________ >>> LLVM Developers mailing list >>> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev >>> >> >> _______________________________________________ >> LLVM Developers mailing list >> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
On Mon, 2008-10-20 at 08:07 -0700, Evan Cheng wrote:> On Oct 20, 2008, at 7:10 AM, sanjiv gupta wrote: > > >>> > >>> PR2916 filed. > >>> Though I did not quite understand why this could be a tablegen bug? > >> > >> > >> Based on your comments. :-) It should be possible to specify two FSR0 > >> sub-registers (FSR0L, FSR0H of the same register class FSR8) with the > >> workaround you described: > >> > >> > >> def FSR16: RegisterClass <"PIC16", [i16], 8, [FSR0, FSR1]> { > >> let SubRegClassList = [FSR8, FSR8]; // HERE. > >> } > >> > > It is currently possible. > > I am confused. Is what you described in PR2916 an issue or not? >is specifying the same subregclass two times okay? or do we need to cleanup the implementation so that you specify a SubRegClass only once. The other related issue is that we can not use SubIdx starting from Zero. - Sanjiv> Evan > > > > > > > - Sanjiv > > > >> > >> Evan > >> > >>> > >>> > >>> - Sanjiv > >>> > >>> > >>> _______________________________________________ > >>> LLVM Developers mailing list > >>> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev > >>> > >> > >> _______________________________________________ > >> LLVM Developers mailing list > >> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > >> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev > > _______________________________________________ > > LLVM Developers mailing list > > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev