similar to: Regex: workaround for variable length negative lookbehind

Displaying 20 results from an estimated 700 matches similar to: "Regex: workaround for variable length negative lookbehind"

2016 Dec 13
2
AD, 4.5.0, DRS or deletion question
Hi all, I have a strange behaviour on our AD. DC=ForestDnsZones,DC=ad,DC=domain,DC=tld Authentification\DC208 via RPC DSA object GUID: 20f711ed-cb02-4543-badb-28d3ed4c4ae1 Last attempt @ NTTIME(0) was successful 0 consecutive failure(s). Last success @ NTTIME(0) DC=ForestDnsZones,DC=ad,DC=domain,DC=tld NTDS DN:
2008 Nov 17
2
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
I have a very strange and complicate H/W platform. It has many registers in one format. The register format is: ------------------------------ ---------------------------------------------------------------------------------------- | 24-bit | 24-bit | 24-bit | 24-bit |
2008 Nov 18
0
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
Why not model each channel as a separate physical register? Evan On Nov 17, 2008, at 6:36 AM, Wei wrote: > I have a very strange and complicate H/W platform. > It has many registers in one format. > The register format is: > > ------------------------------ > ---------------------------------------------------------------------------------------- > | 24-bit
2009 Jan 18
8
regex -> negate a word
Dear all, let's assume I have a vector of character strings: x <- c("abcdef", "defabc", "qwerty") What I would like to find is the following: all elements where the word 'abc' does not appear (i.e. 3 in this case of 'x'). Since I am not really experienced with regular expressions, I started slowly and thought I find all word were
2008 Nov 20
4
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
Because each channel contains 24-bit, so.. what is the llvm::SimpleValueType I should use for each channel? the current llvm::SimpleValueType contains i1, i8, i16, i32, i64, f32, f64, f80, none of them are fit one channel (24-bit). I think I can use i32 or f32 to represent each 24-bit channel, if the runtime result of some machine instructions exceeds 23-bit (1 bit is for sign), then it is an
2008 Nov 21
0
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
24 bit is not unusual in the DSP world. I suppose int == 24 bit integer for some of these chips? There isn't a i24 simple type. However, you can create an extended integer type. See getExtendedIntegerVT. It's almost guaranteed you will have to change a chunk of target independent codegen to support the use of an extended type though. Evan On Nov 20, 2008, at 4:46 AM, Wei wrote:
2008 Feb 03
4
Extract vowels and consonants using Ruby Regex
Hello, I am trying to build a regex to extract vowels and consonants from a string. So far, I am able to extract the basic a-e-i-o-u sequence using the following extension to the String class: class String def vowels scan(/[aeiou]/i) end def consonants scan(/[^aeiou]/i) end end examples: >> "Mary had a little lamb".vowels => aaaiea >> "Mary had a
2015 Mar 29
0
Help! How to make Asterisk support ICE in public network
Hi friends, I am just starting use asterisk for our VoIP server. It works fine in LAN. But when it is deployed in public network(with a public IP), the SIP clients in different NAT fails to communicate with each other. I have set 'icesupport' to 'yes' in sip.conf and set STURN and TURN server in rtp.conf. It still fails! Hope someone to help me out! Thanks in advance:) This
2008 Nov 20
0
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
This is similar to ATI's R300/R420 pixel shaders. I'm familiar with this hardware, but not really an LLVM expert (working on a code generator myself, but learning as I go). Do you have 24-bit integer operations, or just floating point? What about load/store? Are you looking to run large C programs with complex data structures, or just comparatively simple math functions (i.e. a
2008 Nov 22
2
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
Do you mean MVT::getIntegerVT? Because I can not find getExtendedIntegerVT in the llvm source codes. I am excited seeing this function, however I have the following more questions. 1) You mention I will have to change not small amount of target indenpendent codegen codes to support this extended type. Are there any document to describe how to do such kind modification? I see there is a
2011 Mar 08
2
[LLVMdev] How to make release branch available in git (topic changed)
On 03/07/2011 08:30 PM, Anton Korobeynikov wrote: > Hi David > >> I think the trouble with branches is the lockdown of the root repository >> directory. > Surely not (at the server) > >> git svn init --stdlayout https://<user>@llvm.org/svn/llvm-project/llvm \ >>
2011 Mar 10
0
[LLVMdev] How to make release branch available in git (topic changed)
Hi Tobias, > The following expression e.g. > > /^.*(?<!trunk|RELEASE_2.).$/m > > uses lookbehind to matches on: Thanks. Clever trick, but... Variable length lookbehind not implemented in regex m/^.*(?<!trunk|RELEASE_2.).$/ at /usr/lib/git-core/git-svn line 4078. :( -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State
2008 Nov 22
2
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
I have 24-bit integer operations as well as 24-bit floating point (s7.16) operations. The H/W supports load/store instructions, however, they does suggest us not to use these load/store instructions besides debugging purpose. That is to say, you can imagine we don't have load/store instructions, we don't have memory, we just have registers. I will run OpenGL shading laugnage programs on
2008 Oct 26
4
odd behaviour of identical
given what ?identical says, i find the following odd: x = 1:10 y = 1:10 all.equal(x,y) [1] TRUE identical(x,y) [1] TRUE y[11] = 11 y = y[1:10] all.equal(x,y) [1] TRUE identical(x,y) [1] FALSE y [1] 1 2 3 4 5 6 7 8 9 10 length(y) [1] 10 looks like a bug. platform i686-pc-linux-gnu arch i686 os linux-gnu system
2008 Nov 17
4
functional (?) programming in r
the following is a trivialized version of some functional code i tried to use in r: (funcs = lapply(1:5, function(i) function() i)) # a list of no-parameter functions, each with its own closure environment, # each supposed to return the corresponding index when applied to no arguments sapply(funcs, function(func) func()) # supposed to return c(1,2,3,4,5) there is absolutely nothing unusual in
2016 Dec 15
0
AD, 4.5.0, DRS or deletion question
No answer from anyone from the community so I managed by myself, answering also questions by myself. So... Question 1: How can a DC relies on deleted object to perform replication? That is a bug from Samba (the new KCC?). Sorry to say that but what else? Deleted object are objects which are not in use. They have something to do perhaps with replication but they MUST NOT be used as valid source
2017 Jul 19
2
[ovirt-users] ovirt 4.1 hosted engine hyper converged on glusterfs 3.8.10 : "engine" storage domain alway complain about "unsynced" elements
[Adding gluster-users] On Wed, Jul 19, 2017 at 2:52 PM, yayo (j) <jaganz at gmail.com> wrote: > Hi all, > > We have an ovirt cluster hyperconverged with hosted engine on 3 full > replicated node . This cluster have 2 gluster volume: > > - data: volume for the Data (Master) Domain (For vm) > - engine: volume fro the hosted_storage Domain (for hosted engine) > >
2009 May 13
3
where does the null come from?
m = matrix(1:4, 2) apply(m, 1, cat, '\n') # 1 2 # 3 4 # NULL why the null? vQ
2009 Jan 02
1
[Fwd: Re: [R] Randomly remove condition-selected rows from a matrix]
Following Duncan's suggestion, I forward the below to R-devel. vQ -------- Original Message -------- Subject: Re: [R] Randomly remove condition-selected rows from a matrix Date: Fri, 02 Jan 2009 10:34:52 -0500 From: Duncan Murdoch <murdoch at stats.uwo.ca> To: Wacek Kusnierczyk <Waclaw.Marcin.Kusnierczyk at idi.ntnu.no> CC: R help <R-help at stat.math.ethz.ch>
2008 Nov 22
0
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
On Nov 22, 2008, at 11:03 AM, Wei wrote: > I have 24-bit integer operations as well as 24-bit floating point > (s7.16) operations. > > The H/W supports load/store instructions, however, they does suggest > us not to use these load/store instructions besides debugging purpose. > That is to say, you can imagine we don't have load/store instructions, > we don't have